📄 conter8.tan.rpt
字号:
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+------------+------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; 74390:1|32 ; 74390:1|32 ; enb ; enb ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|33 ; 74390:1|33 ; enb ; enb ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|34 ; 74390:1|34 ; enb ; enb ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|31 ; 74390:1|31 ; enb ; enb ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|33 ; 74390:1|31 ; enb ; enb ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|32 ; 74390:1|31 ; enb ; enb ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|5 ; 74390:1|5 ; enb ; enb ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|6 ; 74390:1|6 ; enb ; enb ; None ; None ; 8.000 ns ;
+------------------------------------------+------------+------------+------------+----------+----------------------------+----------------------------+--------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clk' ;
+------------------------------------------+------------+------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+------------+------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; 74390:1|32 ; 74390:1|32 ; clk ; clk ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|33 ; 74390:1|33 ; clk ; clk ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|34 ; 74390:1|34 ; clk ; clk ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|31 ; 74390:1|31 ; clk ; clk ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|33 ; 74390:1|31 ; clk ; clk ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|32 ; 74390:1|31 ; clk ; clk ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|5 ; 74390:1|5 ; clk ; clk ; None ; None ; 8.000 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:1|6 ; 74390:1|6 ; clk ; clk ; None ; None ; 8.000 ns ;
+------------------------------------------+------------+------------+------------+----------+----------------------------+----------------------------+--------------------------+
+--------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------------+------+------------+
; N/A ; None ; 119.000 ns ; 74390:1|32 ; cout ; clk ;
; N/A ; None ; 119.000 ns ; 74390:1|32 ; cout ; enb ;
; N/A ; None ; 110.000 ns ; 74390:1|33 ; cout ; clk ;
; N/A ; None ; 110.000 ns ; 74390:1|33 ; cout ; enb ;
; N/A ; None ; 110.000 ns ; 74390:1|32 ; q[6] ; clk ;
; N/A ; None ; 110.000 ns ; 74390:1|32 ; q[6] ; enb ;
; N/A ; None ; 101.000 ns ; 74390:1|33 ; q[5] ; clk ;
; N/A ; None ; 101.000 ns ; 74390:1|33 ; q[5] ; enb ;
; N/A ; None ; 93.000 ns ; 74390:1|31 ; cout ; clk ;
; N/A ; None ; 93.000 ns ; 74390:1|31 ; cout ; enb ;
; N/A ; None ; 84.000 ns ; 74390:1|34 ; cout ; clk ;
; N/A ; None ; 84.000 ns ; 74390:1|34 ; cout ; enb ;
; N/A ; None ; 84.000 ns ; 74390:1|31 ; q[7] ; clk ;
; N/A ; None ; 84.000 ns ; 74390:1|31 ; q[7] ; enb ;
; N/A ; None ; 75.000 ns ; 74390:1|34 ; q[4] ; clk ;
; N/A ; None ; 75.000 ns ; 74390:1|34 ; q[4] ; enb ;
; N/A ; None ; 67.000 ns ; 74390:1|5 ; cout ; clk ;
; N/A ; None ; 67.000 ns ; 74390:1|5 ; cout ; enb ;
; N/A ; None ; 58.000 ns ; 74390:1|6 ; cout ; clk ;
; N/A ; None ; 58.000 ns ; 74390:1|6 ; cout ; enb ;
; N/A ; None ; 58.000 ns ; 74390:1|5 ; q[2] ; clk ;
; N/A ; None ; 58.000 ns ; 74390:1|5 ; q[2] ; enb ;
; N/A ; None ; 49.000 ns ; 74390:1|6 ; q[1] ; clk ;
; N/A ; None ; 49.000 ns ; 74390:1|6 ; q[1] ; enb ;
; N/A ; None ; 41.000 ns ; 74390:1|3 ; cout ; clk ;
; N/A ; None ; 41.000 ns ; 74390:1|3 ; cout ; enb ;
; N/A ; None ; 32.000 ns ; 74390:1|7 ; cout ; clk ;
; N/A ; None ; 32.000 ns ; 74390:1|7 ; cout ; enb ;
; N/A ; None ; 32.000 ns ; 74390:1|3 ; q[3] ; clk ;
; N/A ; None ; 32.000 ns ; 74390:1|3 ; q[3] ; enb ;
; N/A ; None ; 23.000 ns ; 74390:1|7 ; q[0] ; clk ;
; N/A ; None ; 23.000 ns ; 74390:1|7 ; q[0] ; enb ;
+-------+--------------+------------+------------+------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Tue May 15 11:02:06 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off conter8 -c conter8
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "enb" is an undefined clock
Info: Assuming node "clk" is an undefined clock
Warning: Found 11 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "74390:1|31" as buffer
Info: Detected gated clock "10~7" as buffer
Info: Detected ripple clock "74390:1|7" as buffer
Info: Detected gated clock "74390:1|20~7" as buffer
Info: Detected ripple clock "74390:1|6" as buffer
Info: Detected ripple clock "74390:1|5" as buffer
Info: Detected ripple clock "74390:1|3" as buffer
Info: Detected gated clock "0~9" as buffer
Info: Detected ripple clock "74390:1|34" as buffer
Info: Detected gated clock "74390:1|29~7" as buffer
Info: Detected ripple clock "74390:1|33" as buffer
Info: Clock "enb" has Internal fmax of 13.51 MHz between source register "74390:1|32" and destination register "74390:1|31" (period= 74.0 ns)
Info: + Longest register to register delay is 8.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC6; Fanout = 4; REG Node = '74390:1|31'
Info: Total cell delay = 6.000 ns ( 75.00 % )
Info: Total interconnect delay = 2.000 ns ( 25.00 % )
Info: - Smallest clock skew is -61.000 ns
Info: + Shortest clock path from clock "enb" to destination register is 44.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_33; Fanout = 1; CLK Node = 'enb'
Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = '10~7'
Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC17; Fanout = 6; REG Node = '74390:1|7'
Info: 4: + IC(2.000 ns) + CELL(8.000 ns) = 29.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = '0~9'
Info: 5: + IC(0.000 ns) + CELL(7.000 ns) = 36.000 ns; Loc. = LC13; Fanout = 5; REG Node = '74390:1|34'
Info: 6: + IC(2.000 ns) + CELL(6.000 ns) = 44.000 ns; Loc. = LC6; Fanout = 4; REG Node = '74390:1|31'
Info: Total cell delay = 38.000 ns ( 86.36 % )
Info: Total interconnect delay = 6.000 ns ( 13.64 % )
Info: - Longest clock path from clock "enb" to source register is 105.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_33; Fanout = 1; CLK Node = 'enb'
Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = '10~7'
Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC17; Fanout = 6; REG Node = '74390:1|7'
Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 28.000 ns; Loc. = LC14; Fanout = 5; REG Node = '74390:1|3'
Info: 5: + IC(2.000 ns) + CELL(8.000 ns) = 38.000 ns; Loc. = SEXP6; Fanout = 1; COMB Node = '74390:1|20~7'
Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 45.000 ns; Loc. = LC11; Fanout = 6; REG Node = '74390:1|6'
Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 54.000 ns; Loc. = LC16; Fanout = 5; REG Node = '74390:1|5'
Info: 8: + IC(2.000 ns) + CELL(8.000 ns) = 64.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = '0~9'
Info: 9: + IC(0.000 ns) + CELL(7.000 ns) = 71.000 ns; Loc. = LC13; Fanout = 5; REG Node = '74390:1|34'
Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 80.000 ns; Loc. = LC6; Fanout = 4; REG Node = '74390:1|31'
Info: 11: + IC(2.000 ns) + CELL(8.000 ns) = 90.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = '74390:1|29~7'
Info: 12: + IC(0.000 ns) + CELL(7.000 ns) = 97.000 ns; Loc. = LC5; Fanout = 5; REG Node = '74390:1|33'
Info: 13: + IC(2.000 ns) + CELL(6.000 ns) = 105.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
Info: Total cell delay = 89.000 ns ( 84.76 % )
Info: Total interconnect delay = 16.000 ns ( 15.24 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Micro setup delay of destination is 4.000 ns
Info: Clock "clk" has Internal fmax of 13.51 MHz between source register "74390:1|32" and destination register "74390:1|31" (period= 74.0 ns)
Info: + Longest register to register delay is 8.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC6; Fanout = 4; REG Node = '74390:1|31'
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -