ft_top.fit.eqn

用quartus6原理编辑方式写的简易频率计我自己的实验来的 保证能使请您认真查看谢谢

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--G1_16 is tf_ctro:18|7493:2|16 at LC28
G1_16_reg_input = VCC;
G1_16 = TFFE(G1_16_reg_input, !GLOBAL(CLK), , , );


--G1_15 is tf_ctro:18|7493:2|15 at LC26
G1_15_reg_input = VCC;
G1_15 = TFFE(G1_15_reg_input, !G1_16, , , );


--G1_14 is tf_ctro:18|7493:2|14 at LC23
G1_14_or_out = G1_15;
G1_14_reg_input = G1_14_or_out;
G1_14 = TFFE(G1_14_reg_input, !G1_16, , , );


--G1_13 is tf_ctro:18|7493:2|13 at LC22
G1_13_p1_out = G1_14 & G1_15;
G1_13_or_out = G1_13_p1_out;
G1_13_reg_input = G1_13_or_out;
G1_13 = TFFE(G1_13_reg_input, !G1_16, , , );


--E1L1 is tf_ctro:18|7~68 at LC20
E1L1_p0_out = !G1_14 & G1_13 & G1_15 & !G1_16;
E1L1_p1_out = E1L1 & G1_14;
E1L1_p2_out = E1L1 & !G1_13;
E1L1_p3_out = E1L1 & G1_15;
E1L1_p4_out = E1L1 & !G1_16;
E1L1_or_out = E1L1_p0_out # E1L1_p1_out # E1L1_p2_out # E1L1_p3_out # E1L1_p4_out;
E1L1 = E1L1_or_out;


--E1L2 is tf_ctro:18|16~70 at LC18
E1L2_p0_out = G1_14 & G1_13 & G1_15 & !G1_16;
E1L2_p1_out = E1L2 & !G1_14;
E1L2_p2_out = E1L2 & !G1_13;
E1L2_p3_out = E1L2 & G1_15;
E1L2_p4_out = E1L2 & !G1_16;
E1L2_or_out = E1L2_p0_out # E1L2_p1_out # E1L2_p2_out # E1L2_p3_out # E1L2_p4_out;
E1L2 = E1L2_or_out;


--F1_32 is conter8:13|74390:1|32 at LC16
F1_32_reg_input = VCC;
F1_32 = TFFE(F1_32_reg_input, !F1_33, E1L2, , );


--F1_7 is conter8:13|74390:1|7 at LC30
F1_7_reg_input = VCC;
F1_7 = TFFE(F1_7_reg_input, D1L2, E1L2, , );


--D1L2 is conter8:13|10~7 at SEXP17
D1L2 = EXP(!G1_13 & F_IN);


--C1_19 is 74374:4|19 at LC15
C1_19_or_out = F1_32;
C1_19_reg_input = C1_19_or_out;
C1_19 = DFFE(C1_19_reg_input, !E1L1, , , );


--C1_13 is 74374:4|13 at LC14
C1_13_or_out = F1_7;
C1_13_reg_input = C1_13_or_out;
C1_13 = DFFE(C1_13_reg_input, !E1L1, , , );


--F1_6 is conter8:13|74390:1|6 at LC13
F1_6_reg_input = VCC;
F1_6 = TFFE(F1_6_reg_input, F1L5, E1L2, , );


--F1L5 is conter8:13|74390:1|20~7 at SEXP2
F1L5 = EXP(!F1_3 & F1_7);


--F1_5 is conter8:13|74390:1|5 at LC11
F1_5_reg_input = VCC;
F1_5 = TFFE(F1_5_reg_input, !F1_6, E1L2, , );


--C1_14 is 74374:4|14 at LC10
C1_14_or_out = F1_6;
C1_14_reg_input = C1_14_or_out;
C1_14 = DFFE(C1_14_reg_input, !E1L1, , , );


--C1_15 is 74374:4|15 at LC9
C1_15_or_out = F1_5;
C1_15_reg_input = C1_15_or_out;
C1_15 = DFFE(C1_15_reg_input, !E1L1, , , );


--F1_3 is conter8:13|74390:1|3 at LC7
F1_3_p1_out = !F1_3 & F1_5 & F1_6;
F1_3_or_out = F1_3_p1_out;
F1_3_reg_input = F1_3_or_out;
F1_3 = DFFE(F1_3_reg_input, !F1_7, E1L2, , );


--C1_16 is 74374:4|16 at LC5
C1_16_or_out = F1_3;
C1_16_reg_input = C1_16_or_out;
C1_16 = DFFE(C1_16_reg_input, !E1L1, , , );


--B1L3 is 74248:2|90~18 at LC29
B1L3_p1_out = !C1_13 & C1_14;
B1L3_p2_out = !C1_13 & !C1_15;
B1L3_or_out = B1L3_p1_out # B1L3_p2_out;
B1L3 = B1L3_or_out;


--F1_34 is conter8:13|74390:1|34 at LC1
F1_34_reg_input = VCC;
F1_34 = TFFE(F1_34_reg_input, D1L1, E1L2, , );


--D1L1 is conter8:13|0~9 at SEXP3
D1L1 = EXP(F1_3 & !F1_5 & !F1_6 & F1_7);


--F1_31 is conter8:13|74390:1|31 at LC2
F1_31_p1_out = F1_33 & !F1_31 & F1_32;
F1_31_or_out = F1_31_p1_out;
F1_31_reg_input = F1_31_or_out;
F1_31 = DFFE(F1_31_reg_input, !F1_34, E1L2, , );


--C1_17 is 74374:4|17 at LC4
C1_17_or_out = F1_34;
C1_17_reg_input = C1_17_or_out;
C1_17 = DFFE(C1_17_reg_input, !E1L1, , , );


--B1L5 is 74248:2|92~46 at LC17
B1L5_p1_out = !C1_16 & C1_15;
B1L5_p2_out = !C1_15 & !C1_14;
B1L5_p3_out = !C1_15 & C1_13;
B1L5_or_out = B1L5_p1_out # B1L5_p2_out # B1L5_p3_out;
B1L5 = B1L5_or_out;


--B1L6 is 74248:2|93~64 at LC19
B1L6_p1_out = !C1_16 & !C1_15;
B1L6_p2_out = !C1_16 & C1_14 & C1_13;
B1L6_p3_out = !C1_15 & !C1_14;
B1L6_p4_out = !C1_14 & !C1_13;
B1L6_or_out = B1L6_p1_out # B1L6_p2_out # B1L6_p3_out # B1L6_p4_out;
B1L6 = B1L6_or_out;


--C1_20 is 74374:4|20 at LC6
C1_20_or_out = F1_31;
C1_20_reg_input = C1_20_or_out;
C1_20 = DFFE(C1_20_reg_input, !E1L1, , , );


--B1L1 is 74248:2|88~79 at LC21
B1L1_p1_out = C1_15 & !C1_14;
B1L1_p2_out = !C1_14 & C1_16;
B1L1_p3_out = !C1_15 & C1_14;
B1L1_p4_out = C1_14 & !C1_13;
B1L1_or_out = B1L1_p1_out # B1L1_p2_out # B1L1_p3_out # B1L1_p4_out;
B1L1 = B1L1_or_out;


--F1_33 is conter8:13|74390:1|33 at LC8
F1_33_reg_input = VCC;
F1_33 = TFFE(F1_33_reg_input, F1L6, E1L2, , );


--F1L6 is conter8:13|74390:1|29~7 at SEXP1
F1L6 = EXP(F1_34 & !F1_31);


--B1L2 is 74248:2|89~63 at LC24
B1L2_p1_out = C1_15 & !C1_13;
B1L2_p2_out = C1_15 & !C1_14;
B1L2_p3_out = !C1_14 & C1_16;
B1L2_p4_out = !C1_13 & !C1_14;
B1L2_or_out = B1L2_p1_out # B1L2_p2_out # B1L2_p3_out # B1L2_p4_out;
B1L2 = B1L2_or_out;


--B1L4 is 74248:2|91~66 at LC25
B1L4_p0_out = !C1_13 & !C1_15;
B1L4_p1_out = C1_14 & !C1_13;
B1L4_p2_out = !C1_14 & C1_13 & C1_15;
B1L4_p3_out = C1_14 & !C1_15;
B1L4_p4_out = !C1_15 & C1_16;
B1L4_or_out = B1L4_p0_out # B1L4_p1_out # B1L4_p2_out # B1L4_p3_out # B1L4_p4_out;
B1L4 = B1L4_or_out;


--D1L3 is conter8:13|19~10 at LC3
D1L3_p1_out = F1_34 & !F1_33 & F1_31 & !F1_32 & F1_3 & !F1_5 & !F1_6 & F1_7;
D1L3_or_out = D1L3_p1_out;
D1L3 = D1L3_or_out;


--C1_18 is 74374:4|18 at LC12
C1_18_or_out = F1_33;
C1_18_reg_input = C1_18_or_out;
C1_18 = DFFE(C1_18_reg_input, !E1L1, , , );


--B1L7 is 74248:2|94~151 at LC27
B1L7_p1_out = !C1_16 & C1_14;
B1L7_p2_out = !C1_14 & C1_15 & C1_13;
B1L7_p3_out = C1_16 & !C1_14 & !C1_15;
B1L7_p4_out = !C1_14 & !C1_15 & !C1_13;
B1L7_or_out = B1L7_p1_out # B1L7_p2_out # B1L7_p3_out # B1L7_p4_out;
B1L7 = B1L7_or_out;


--B2L2 is 74248:5|89~63 at LC35
B2L2_p1_out = C1_19 & !C1_17;
B2L2_p2_out = C1_19 & !C1_18;
B2L2_p3_out = !C1_18 & C1_20;
B2L2_p4_out = !C1_17 & !C1_18;
B2L2_or_out = B2L2_p1_out # B2L2_p2_out # B2L2_p3_out # B2L2_p4_out;
B2L2 = B2L2_or_out;


--B2L3 is 74248:5|90~18 at LC37
B2L3_p1_out = !C1_17 & C1_18;
B2L3_p2_out = !C1_17 & !C1_19;
B2L3_or_out = B2L3_p1_out # B2L3_p2_out;
B2L3 = B2L3_or_out;


--B2L1 is 74248:5|88~79 at LC38
B2L1_p1_out = C1_19 & !C1_18;
B2L1_p2_out = !C1_18 & C1_20;
B2L1_p3_out = !C1_19 & C1_18;
B2L1_p4_out = C1_18 & !C1_17;
B2L1_or_out = B2L1_p1_out # B2L1_p2_out # B2L1_p3_out # B2L1_p4_out;
B2L1 = B2L1_or_out;


--B2L4 is 74248:5|91~66 at LC40
B2L4_p0_out = !C1_17 & !C1_19;
B2L4_p1_out = C1_18 & !C1_17;
B2L4_p2_out = !C1_18 & C1_17 & C1_19;
B2L4_p3_out = C1_18 & !C1_19;
B2L4_p4_out = !C1_19 & C1_20;
B2L4_or_out = B2L4_p0_out # B2L4_p1_out # B2L4_p2_out # B2L4_p3_out # B2L4_p4_out;
B2L4 = B2L4_or_out;


--B2L5 is 74248:5|92~46 at LC43
B2L5_p1_out = !C1_20 & C1_19;
B2L5_p2_out = !C1_19 & !C1_18;
B2L5_p3_out = !C1_19 & C1_17;
B2L5_or_out = B2L5_p1_out # B2L5_p2_out # B2L5_p3_out;
B2L5 = B2L5_or_out;


--B2L7 is 74248:5|94~151 at LC45
B2L7_p1_out = !C1_20 & C1_18;
B2L7_p2_out = !C1_18 & C1_19 & C1_17;
B2L7_p3_out = C1_20 & !C1_18 & !C1_19;
B2L7_p4_out = !C1_18 & !C1_19 & !C1_17;
B2L7_or_out = B2L7_p1_out # B2L7_p2_out # B2L7_p3_out # B2L7_p4_out;
B2L7 = B2L7_or_out;


--B2L6 is 74248:5|93~80 at LC46
B2L6_p1_out = !C1_20 & !C1_19;
B2L6_p2_out = !C1_20 & C1_18 & C1_17;
B2L6_p3_out = !C1_19 & !C1_18;
B2L6_p4_out = !C1_18 & !C1_17;
B2L6_or_out = B2L6_p1_out # B2L6_p2_out # B2L6_p3_out # B2L6_p4_out;
B2L6 = B2L6_or_out;


--CLK is CLK at PIN_83
--operation mode is input

CLK = INPUT();


--F_IN is F_IN at PIN_52
--operation mode is input

F_IN = INPUT();


--L[4] is L[4] at PIN_15
--operation mode is output

L[4] = OUTPUT(B1L3);


--L[2] is L[2] at PIN_22
--operation mode is output

L[2] = OUTPUT(B1L5);


--L[1] is L[1] at PIN_21
--operation mode is output

L[1] = OUTPUT(B1L6);


--L[6] is L[6] at PIN_20
--operation mode is output

L[6] = OUTPUT(B1L1);


--L[5] is L[5] at PIN_18
--operation mode is output

L[5] = OUTPUT(B1L2);


--L[3] is L[3] at PIN_17
--operation mode is output

L[3] = OUTPUT(B1L4);


--COUT is COUT at PIN_12
--operation mode is output

COUT = OUTPUT(D1L3);


--L[0] is L[0] at PIN_16
--operation mode is output

L[0] = OUTPUT(B1L7);


--H[6] is H[6] at PIN_29
--operation mode is output

H[6] = OUTPUT(B2L1);


--H[5] is H[5] at PIN_31
--operation mode is output

H[5] = OUTPUT(B2L2);


--H[4] is H[4] at PIN_30
--operation mode is output

H[4] = OUTPUT(B2L3);


--H[3] is H[3] at PIN_28
--operation mode is output

H[3] = OUTPUT(B2L4);


--H[2] is H[2] at PIN_27
--operation mode is output

H[2] = OUTPUT(B2L5);


--H[0] is H[0] at PIN_25
--operation mode is output

H[0] = OUTPUT(B2L7);


--H[1] is H[1] at PIN_24
--operation mode is output

H[1] = OUTPUT(B2L6);