📄 xianshi.rpt
字号:
- 6 - A 21 OR2 s ! 0 2 0 1 ~4179~1
- 7 - A 21 AND2 0 4 0 1 :4179
- 8 - A 21 OR2 0 4 1 0 :4183
- 8 - A 13 OR2 s ! 0 4 0 2 ~4219~1
- 5 - A 13 OR2 0 4 0 2 :4219
- 6 - A 20 OR2 0 3 0 1 :4228
- 3 - A 20 OR2 0 3 1 0 :4234
- 5 - A 21 OR2 0 4 1 0 :4285
- 6 - A 13 OR2 0 4 0 1 :4326
- 4 - A 20 OR2 0 4 1 0 :4336
- 2 - A 21 OR2 0 4 0 2 :4372
- 1 - A 21 OR2 s 0 2 0 5 ~4381~1
- 4 - A 21 OR2 0 3 0 1 :4381
- 3 - A 21 OR2 0 3 1 0 :4387
- 3 - B 18 AND2 0 4 0 7 :4474
- 4 - B 18 OR2 ! 0 4 0 6 :4483
- 2 - B 18 AND2 0 4 0 4 :4492
- 6 - B 18 AND2 0 4 0 4 :4501
- 4 - B 23 AND2 0 2 0 1 :4510
- 6 - B 19 AND2 s 0 3 0 6 ~4519~1
- 5 - B 19 AND2 0 4 0 5 :4528
- 1 - B 19 AND2 0 4 0 6 :4537
- 6 - B 21 AND2 0 4 0 3 :4546
- 5 - B 21 AND2 0 4 0 3 :4555
- 4 - B 21 AND2 0 4 0 5 :4564
- 2 - B 21 OR2 ! 0 4 0 4 :4573
- 2 - B 08 AND2 0 4 0 3 :4582
- 1 - B 08 OR2 ! 0 4 0 4 :4591
- 4 - B 08 AND2 0 4 0 3 :4600
- 3 - B 08 AND2 0 4 0 3 :4609
- 7 - B 14 OR2 0 4 0 1 :4649
- 1 - B 14 OR2 s 0 4 0 1 ~4701~1
- 8 - B 24 AND2 s 0 2 0 1 ~4715~1
- 2 - B 24 OR2 0 4 1 0 :4715
- 3 - B 21 OR2 s 0 2 0 3 ~4740~1
- 4 - B 14 OR2 s 0 2 0 1 ~4740~2
- 1 - B 21 OR2 s 0 4 0 2 ~4740~3
- 2 - B 14 OR2 0 3 0 1 :4748
- 3 - B 24 OR2 0 4 1 0 :4764
- 1 - B 23 OR2 s ! 0 2 0 2 ~4766~1
- 2 - B 17 OR2 0 4 0 1 :4793
- 8 - B 17 OR2 0 4 0 1 :4797
- 7 - B 24 AND2 0 3 0 1 :4811
- 5 - B 24 OR2 0 4 1 0 :4815
- 5 - B 14 OR2 0 4 0 2 :4833
- 1 - B 17 OR2 0 4 0 1 :4850
- 6 - B 23 OR2 0 4 0 1 :4859
- 7 - B 23 OR2 0 4 1 0 :4866
- 1 - B 24 OR2 s 0 2 0 3 ~4908~1
- 6 - B 24 OR2 0 4 0 1 :4908
- 4 - B 24 OR2 0 4 1 0 :4917
- 3 - B 14 OR2 0 4 0 2 :4947
- 3 - B 23 OR2 0 4 0 1 :4958
- 8 - B 23 OR2 0 4 1 0 :4968
- 6 - B 14 OR2 0 4 0 2 :4983
- 8 - B 14 OR2 s 0 4 0 1 ~5004~1
- 2 - B 23 OR2 0 4 0 1 :5012
- 8 - B 15 OR2 s 0 2 0 3 ~5013~1
- 5 - B 23 OR2 0 4 1 0 :5019
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\ss\xianshi.rpt
xianshi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 49/ 96( 51%) 29/ 48( 60%) 34/ 48( 70%) 2/16( 12%) 6/16( 37%) 0/16( 0%)
B: 44/ 96( 45%) 16/ 48( 33%) 30/ 48( 62%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 7/ 48( 14%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\ss\xianshi.rpt
xianshi
** EQUATIONS **
BIN0 : INPUT;
BIN1 : INPUT;
BIN2 : INPUT;
BIN3 : INPUT;
BIN4 : INPUT;
BIN5 : INPUT;
BIN6 : INPUT;
BIN7 : INPUT;
-- Node name is 'getdata0'
-- Equation name is 'getdata0', type is output
getdata0 = _LC5_B18;
-- Node name is 'getdata1'
-- Equation name is 'getdata1', type is output
getdata1 = _LC1_B18;
-- Node name is 'getdata2'
-- Equation name is 'getdata2', type is output
getdata2 = _LC1_B13;
-- Node name is 'getdata3'
-- Equation name is 'getdata3', type is output
getdata3 = _LC4_B13;
-- Node name is 'getdata4'
-- Equation name is 'getdata4', type is output
getdata4 = _LC4_B16;
-- Node name is 'getdata5'
-- Equation name is 'getdata5', type is output
getdata5 = _LC2_B16;
-- Node name is 'getdata6'
-- Equation name is 'getdata6', type is output
getdata6 = _LC3_A22;
-- Node name is 'getdata7'
-- Equation name is 'getdata7', type is output
getdata7 = _LC8_A22;
-- Node name is 'seg10'
-- Equation name is 'seg10', type is output
seg10 = _LC3_A21;
-- Node name is 'seg11'
-- Equation name is 'seg11', type is output
seg11 = _LC4_A20;
-- Node name is 'seg12'
-- Equation name is 'seg12', type is output
seg12 = _LC5_A21;
-- Node name is 'seg13'
-- Equation name is 'seg13', type is output
seg13 = _LC3_A20;
-- Node name is 'seg14'
-- Equation name is 'seg14', type is output
seg14 = _LC8_A21;
-- Node name is 'seg15'
-- Equation name is 'seg15', type is output
seg15 = _LC7_A20;
-- Node name is 'seg16'
-- Equation name is 'seg16', type is output
seg16 = _LC1_A20;
-- Node name is 'seg20'
-- Equation name is 'seg20', type is output
seg20 = _LC5_B23;
-- Node name is 'seg21'
-- Equation name is 'seg21', type is output
seg21 = _LC8_B23;
-- Node name is 'seg22'
-- Equation name is 'seg22', type is output
seg22 = _LC4_B24;
-- Node name is 'seg23'
-- Equation name is 'seg23', type is output
seg23 = _LC7_B23;
-- Node name is 'seg24'
-- Equation name is 'seg24', type is output
seg24 = _LC5_B24;
-- Node name is 'seg25'
-- Equation name is 'seg25', type is output
seg25 = _LC3_B24;
-- Node name is 'seg26'
-- Equation name is 'seg26', type is output
seg26 = _LC2_B24;
-- Node name is '~131~1'
-- Equation name is '~131~1', location is LC5_A9, type is buried.
-- synthesized logic cell
_LC5_A9 = LCELL( _EQ001);
_EQ001 = BIN7
# BIN5
# BIN0;
-- Node name is '~131~2'
-- Equation name is '~131~2', location is LC7_A8, type is buried.
-- synthesized logic cell
_LC7_A8 = LCELL( _EQ002);
_EQ002 = BIN2
# BIN3
# _LC5_A9;
-- Node name is '~140~1'
-- Equation name is '~140~1', location is LC6_A9, type is buried.
-- synthesized logic cell
!_LC6_A9 = _LC6_A9~NOT;
_LC6_A9~NOT = LCELL( _EQ003);
_EQ003 = BIN0 & !BIN5 & !BIN7;
-- Node name is '~140~2'
-- Equation name is '~140~2', location is LC7_A9, type is buried.
-- synthesized logic cell
!_LC7_A9 = _LC7_A9~NOT;
_LC7_A9~NOT = LCELL( _EQ004);
_EQ004 = !BIN2 & !BIN3 & !_LC6_A9;
-- Node name is '~185~1'
-- Equation name is '~185~1', location is LC2_A8, type is buried.
-- synthesized logic cell
_LC2_A8 = LCELL( _EQ005);
_EQ005 = _LC5_A9
# !BIN2
# BIN3;
-- Node name is ':221'
-- Equation name is '_LC3_B5', type is buried
!_LC3_B5 = _LC3_B5~NOT;
_LC3_B5~NOT = LCELL( _EQ006);
_EQ006 = _LC3_A8
# _LC2_B11;
-- Node name is ':230'
-- Equation name is '_LC4_B5', type is buried
_LC4_B5 = LCELL( _EQ007);
_EQ007 = !_LC2_A9 & !_LC2_B11;
-- Node name is ':239'
-- Equation name is '_LC7_B3', type is buried
!_LC7_B3 = _LC7_B3~NOT;
_LC7_B3~NOT = LCELL( _EQ008);
_EQ008 = _LC4_A8
# _LC5_B11;
-- Node name is '~248~1'
-- Equation name is '~248~1', location is LC5_B11, type is buried.
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