📄 counter.rpt
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-- Node name is 'SJXSH2'
-- Equation name is 'SJXSH2', type is output
SJXSH2 = linshi12;
-- Node name is 'SJXSH3'
-- Equation name is 'SJXSH3', type is output
SJXSH3 = linshi13;
-- Node name is 'SJXSH4'
-- Equation name is 'SJXSH4', type is output
SJXSH4 = linshi14;
-- Node name is 'SJXSH5'
-- Equation name is 'SJXSH5', type is output
SJXSH5 = linshi15;
-- Node name is 'SJXSH6'
-- Equation name is 'SJXSH6', type is output
SJXSH6 = linshi16;
-- Node name is 'SJXSH7'
-- Equation name is 'SJXSH7', type is output
SJXSH7 = linshi17;
-- Node name is 'tJ'
-- Equation name is 'tJ', type is output
tJ = _LC3_A22;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_A16', type is buried
_LC7_A16 = LCELL( _EQ013);
_EQ013 = linshi11
# linshi10
# linshi12;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_A16', type is buried
_LC8_A16 = LCELL( _EQ014);
_EQ014 = linshi13
# linshi12
# linshi11
# linshi10;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = LCELL( _EQ015);
_EQ015 = linshi15
# linshi14
# _LC8_A16;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = LCELL( _EQ016);
_EQ016 = linshi16
# _LC2_A14;
-- Node name is '|LPM_ADD_SUB:314|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A13', type is buried
_LC2_A13 = LCELL( _EQ017);
_EQ017 = linshi20 & linshi21;
-- Node name is '|LPM_ADD_SUB:314|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A13', type is buried
_LC6_A13 = LCELL( _EQ018);
_EQ018 = linshi20 & linshi21 & linshi22;
-- Node name is '|LPM_ADD_SUB:314|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A22', type is buried
_LC1_A22 = LCELL( _EQ019);
_EQ019 = _LC6_A13 & linshi23;
-- Node name is ':19'
-- Equation name is '_LC3_A22', type is buried
_LC3_A22 = DFFE( _EQ020, GLOBAL( clk), VCC, VCC, start);
_EQ020 = _LC3_A22
# _LC6_A22;
-- Node name is ':113'
-- Equation name is '_LC6_A22', type is buried
!_LC6_A22 = _LC6_A22~NOT;
_LC6_A22~NOT = LCELL( _EQ021);
_EQ021 = linshi17
# _LC1_A14;
-- Node name is '~151~1'
-- Equation name is '~151~1', location is LC2_A22, type is buried.
-- synthesized logic cell
_LC2_A22 = LCELL( _EQ022);
_EQ022 = linshi22 & linshi23 & linshi24;
-- Node name is ':151'
-- Equation name is '_LC3_A13', type is buried
_LC3_A13 = LCELL( _EQ023);
_EQ023 = _LC2_A22 & !linshi20 & linshi21;
-- Node name is ':270'
-- Equation name is '_LC7_A14', type is buried
_LC7_A14 = LCELL( _EQ024);
_EQ024 = _LC2_A14 & linshi16
# !_LC2_A14 & _LC3_A13 & !linshi16
# !_LC3_A13 & linshi16;
-- Node name is ':276'
-- Equation name is '_LC4_A14', type is buried
_LC4_A14 = LCELL( _EQ025);
_EQ025 = linshi14 & linshi15
# _LC8_A16 & linshi15
# _LC3_A13 & !_LC8_A16 & !linshi14 & !linshi15
# !_LC3_A13 & linshi15;
-- Node name is ':282'
-- Equation name is '_LC3_A14', type is buried
_LC3_A14 = LCELL( _EQ026);
_EQ026 = _LC8_A16 & linshi14
# _LC3_A13 & !_LC8_A16 & !linshi14
# !_LC3_A13 & linshi14;
-- Node name is ':288'
-- Equation name is '_LC5_A16', type is buried
_LC5_A16 = LCELL( _EQ027);
_EQ027 = _LC7_A16 & linshi13
# _LC3_A13 & !_LC7_A16 & !linshi13
# !_LC3_A13 & linshi13;
-- Node name is ':294'
-- Equation name is '_LC6_A16', type is buried
_LC6_A16 = LCELL( _EQ028);
_EQ028 = linshi11 & linshi12
# linshi10 & linshi12
# _LC3_A13 & !linshi10 & !linshi11 & !linshi12
# !_LC3_A13 & linshi12;
-- Node name is ':300'
-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = LCELL( _EQ029);
_EQ029 = linshi10 & linshi11
# _LC3_A13 & !linshi10 & !linshi11
# !_LC3_A13 & linshi11;
-- Node name is ':379'
-- Equation name is '_LC6_A14', type is buried
_LC6_A14 = LCELL( _EQ030);
_EQ030 = linshi16 & linshi17
# _LC2_A14 & linshi17
# !_LC3_A13 & linshi17;
Project Information d:\ss\counter.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 46,045K
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