📄 zuihou.rpt
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Device-Specific Information: d:\ss\zuihou.rpt
zuihou
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
125 - - - -- INPUT G 0 0 0 0 CLK
55 - - - -- INPUT G 0 0 0 0 CP
54 - - - -- INPUT G 0 0 0 0 LD
56 - - - -- INPUT G 0 0 0 0 SCANCLK
124 - - - -- INPUT G 0 0 0 7 START
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\ss\zuihou.rpt
zuihou
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
102 - - A -- OUTPUT 0 1 0 0 GETDATA0
143 - - A -- OUTPUT 0 1 0 0 GETDATA1
9 - - B -- OUTPUT 0 1 0 0 GETDATA2
69 - - - 06 OUTPUT 0 1 0 0 GETDATA3
101 - - A -- OUTPUT 0 1 0 0 GETDATA4
7 - - A -- OUTPUT 0 1 0 0 GETDATA5
116 - - - 04 OUTPUT 0 1 0 0 GETDATA6
72 - - - 03 OUTPUT 0 1 0 0 GETDATA7
8 - - A -- OUTPUT 0 1 0 0 JISHUDATA0
144 - - A -- OUTPUT 0 1 0 0 JISHUDATA1
11 - - C -- OUTPUT 0 1 0 0 JISHUDATA2
79 - - F -- OUTPUT 0 1 0 0 JISHUDATA3
114 - - - 04 OUTPUT 0 1 0 0 JISHUDATA4
60 - - - 12 OUTPUT 0 1 0 0 JISHUDATA5
121 - - - 10 OUTPUT 0 1 0 0 JISHUDATA6
63 - - - 10 OUTPUT 0 1 0 0 JISHUDATA7
17 - - D -- OUTPUT 0 1 0 0 PAUSE
18 - - D -- OUTPUT 0 1 0 0 REV
19 - - D -- OUTPUT 0 1 0 0 RUN
89 - - C -- OUTPUT 0 1 0 0 SEGOUT0
90 - - C -- OUTPUT 0 1 0 0 SEGOUT1
14 - - C -- OUTPUT 0 1 0 0 SEGOUT2
12 - - C -- OUTPUT 0 1 0 0 SEGOUT3
91 - - C -- OUTPUT 0 1 0 0 SEGOUT4
13 - - C -- OUTPUT 0 1 0 0 SEGOUT5
92 - - C -- OUTPUT 0 1 0 0 SEGOUT6
100 - - A -- OUTPUT 0 1 0 0 SELOUT0
64 - - - 09 OUTPUT 0 1 0 0 SELOUT1
109 - - A -- OUTPUT 0 1 0 0 SELOUT2
88 - - D -- OUTPUT 0 1 0 0 SELOUT3
20 - - D -- OUTPUT 0 1 0 0 TJ
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\ss\zuihou.rpt
zuihou
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - F 20 OR2 0 2 0 3 |COUTER:20|LPM_ADD_SUB:195|addcore:adder|pcarry1
- 1 - F 20 OR2 0 3 0 10 |COUTER:20|LPM_ADD_SUB:195|addcore:adder|pcarry3
- 6 - F 16 OR2 0 2 0 6 |COUTER:20|LPM_ADD_SUB:195|addcore:adder|pcarry4
- 4 - F 22 OR2 0 3 0 1 |COUTER:20|LPM_ADD_SUB:195|addcore:adder|pcarry6
- 4 - C 21 AND2 0 2 0 1 |COUTER:20|LPM_ADD_SUB:314|addcore:adder|:63
- 2 - C 21 AND2 0 3 0 2 |COUTER:20|LPM_ADD_SUB:314|addcore:adder|:67
- 2 - C 23 AND2 0 2 0 1 |COUTER:20|LPM_ADD_SUB:314|addcore:adder|:71
- 4 - D 13 DFFE + 1 1 1 1 |COUTER:20|:19
- 3 - F 22 DFFE + 0 2 0 6 |COUTER:20|linshi17 (|COUTER:20|:21)
- 2 - F 22 DFFE + 0 3 0 7 |COUTER:20|linshi16 (|COUTER:20|:22)
- 2 - F 16 DFFE + 0 3 0 45 |COUTER:20|linshi15 (|COUTER:20|:23)
- 7 - F 16 DFFE + 0 3 0 50 |COUTER:20|linshi14 (|COUTER:20|:24)
- 3 - F 20 DFFE + 0 3 0 26 |COUTER:20|linshi13 (|COUTER:20|:25)
- 4 - F 20 DFFE + 0 3 0 27 |COUTER:20|linshi12 (|COUTER:20|:26)
- 2 - F 20 DFFE + 0 3 0 15 |COUTER:20|linshi11 (|COUTER:20|:27)
- 1 - C 23 DFFE + 0 3 0 13 |COUTER:20|linshi10 (|COUTER:20|:28)
- 3 - C 21 DFFE + 1 2 0 1 |COUTER:20|linshi24 (|COUTER:20|:29)
- 3 - C 23 DFFE + 1 2 0 2 |COUTER:20|linshi23 (|COUTER:20|:30)
- 5 - C 21 DFFE + 1 2 0 2 |COUTER:20|linshi22 (|COUTER:20|:31)
- 6 - C 21 DFFE + 1 2 0 3 |COUTER:20|linshi21 (|COUTER:20|:32)
- 7 - C 21 DFFE + 1 1 0 4 |COUTER:20|linshi20 (|COUTER:20|:33)
- 5 - F 22 OR2 ! 0 4 0 17 |COUTER:20|:113
- 8 - C 21 OR2 s ! 0 3 0 1 |COUTER:20|~151~1
- 1 - C 21 OR2 ! 0 3 0 8 |COUTER:20|:151
- 8 - F 22 OR2 0 4 0 1 |COUTER:20|:270
- 5 - F 16 OR2 0 3 0 1 |COUTER:20|:276
- 4 - F 16 OR2 0 3 0 1 |COUTER:20|:282
- 8 - F 20 OR2 0 4 0 1 |COUTER:20|:288
- 7 - F 20 OR2 0 3 0 1 |COUTER:20|:294
- 6 - F 20 OR2 0 3 0 1 |COUTER:20|:300
- 7 - F 22 OR2 0 4 0 1 |COUTER:20|:379
- 4 - C 23 AND2 0 2 0 14 |JISHU:3|LPM_ADD_SUB:88|addcore:adder|:75
- 1 - E 24 AND2 0 2 0 15 |JISHU:3|LPM_ADD_SUB:88|addcore:adder|:79
- 6 - B 19 AND2 0 3 0 4 |JISHU:3|LPM_ADD_SUB:88|addcore:adder|:87
- 2 - B 19 DFFE + 0 3 0 11 |JISHU:3|:3
- 4 - B 19 DFFE + 0 2 0 28 |JISHU:3|:5
- 1 - B 19 DFFE + 0 1 0 13 |JISHU:3|:7
- 6 - B 15 DFFE + 0 2 0 24 |JISHU:3|:9
- 1 - B 17 DFFE + 0 1 0 18 |JISHU:3|:11
- 1 - E 15 DFFE + 0 1 0 34 |JISHU:3|:13
- 6 - C 23 DFFE + 0 1 0 27 |JISHU:3|:15
- 5 - C 23 DFFE + 0 0 0 11 |JISHU:3|:17
- 7 - D 09 DFFE + 0 3 0 4 |SEVENDUAN:4|q2 (|SEVENDUAN:4|:72)
- 5 - D 09 DFFE + 0 2 0 5 |SEVENDUAN:4|q1 (|SEVENDUAN:4|:73)
- 3 - D 09 DFFE + 0 0 0 6 |SEVENDUAN:4|q0 (|SEVENDUAN:4|:74)
- 4 - D 09 OR2 ! 0 3 1 2 |SEVENDUAN:4|:108
- 6 - D 09 AND2 0 3 1 4 |SEVENDUAN:4|:261
- 2 - D 09 AND2 0 3 1 4 |SEVENDUAN:4|:265
- 1 - D 09 AND2 0 3 1 4 |SEVENDUAN:4|:269
- 2 - C 05 OR2 0 3 0 1 |SEVENDUAN:4|:376
- 3 - C 05 OR2 0 3 0 1 |SEVENDUAN:4|:382
- 1 - C 05 OR2 0 3 0 19 |SEVENDUAN:4|:388
- 2 - C 04 OR2 0 3 0 1 |SEVENDUAN:4|:394
- 3 - C 04 OR2 0 3 0 1 |SEVENDUAN:4|:397
- 1 - C 04 OR2 0 3 0 19 |SEVENDUAN:4|:400
- 3 - A 06 OR2 0 3 0 1 |SEVENDUAN:4|:406
- 7 - A 06 OR2 0 3 0 1 |SEVENDUAN:4|:409
- 1 - A 06 OR2 0 3 0 18 |SEVENDUAN:4|:412
- 7 - A 05 OR2 0 3 0 1 |SEVENDUAN:4|:418
- 8 - A 05 OR2 0 3 0 1 |SEVENDUAN:4|:421
- 1 - A 05 OR2 0 3 0 18 |SEVENDUAN:4|:424
- 1 - C 09 AND2 0 4 0 3 |SEVENDUAN:4|:443
- 6 - C 09 OR2 ! 0 4 0 3 |SEVENDUAN:4|:448
- 1 - C 01 AND2 s 0 2 0 1 |SEVENDUAN:4|~453~1
- 2 - C 09 AND2 0 4 0 2 |SEVENDUAN:4|:453
- 1 - C 03 AND2 0 4 0 1 |SEVENDUAN:4|:473
- 3 - C 07 OR2 ! 0 4 0 2 |SEVENDUAN:4|:478
- 4 - C 03 AND2 0 4 0 1 |SEVENDUAN:4|:483
- 6 - C 03 OR2 ! 0 4 0 1 |SEVENDUAN:4|:488
- 4 - C 01 OR2 0 4 1 0 |SEVENDUAN:4|:624
- 6 - C 07 AND2 s 0 2 0 1 |SEVENDUAN:4|~649~1
- 1 - C 07 OR2 0 4 0 1 |SEVENDUAN:4|:661
- 3 - C 09 OR2 0 4 1 0 |SEVENDUAN:4|:673
- 5 - C 03 OR2 s 0 4 0 1 |SEVENDUAN:4|~694~1
- 8 - C 03 OR2 0 4 0 1 |SEVENDUAN:4|:700
- 3 - C 03 OR2 s 0 4 0 1 |SEVENDUAN:4|~720~1
- 2 - C 03 OR2 0 4 0 1 |SEVENDUAN:4|:720
- 5 - C 09 OR2 0 4 1 0 |SEVENDUAN:4|:724
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