📄 jishu.rpt
字号:
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 3/ 96( 3%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\ss\ss\jishu.rpt
jishu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 cP
Device-Specific Information: f:\ss\ss\jishu.rpt
jishu
** EQUATIONS **
cP : INPUT;
LD : INPUT;
-- Node name is 'JISHUtime0'
-- Equation name is 'JISHUtime0', type is output
JISHUtime0 = _LC8_C8;
-- Node name is 'JISHUtime1'
-- Equation name is 'JISHUtime1', type is output
JISHUtime1 = _LC6_C8;
-- Node name is 'JISHUtime2'
-- Equation name is 'JISHUtime2', type is output
JISHUtime2 = _LC2_C8;
-- Node name is 'JISHUtime3'
-- Equation name is 'JISHUtime3', type is output
JISHUtime3 = _LC4_C8;
-- Node name is 'JISHUtime4'
-- Equation name is 'JISHUtime4', type is output
JISHUtime4 = _LC7_C11;
-- Node name is 'JISHUtime5'
-- Equation name is 'JISHUtime5', type is output
JISHUtime5 = _LC1_C11;
-- Node name is 'JISHUtime6'
-- Equation name is 'JISHUtime6', type is output
JISHUtime6 = _LC5_C11;
-- Node name is 'JISHUtime7'
-- Equation name is 'JISHUtime7', type is output
JISHUtime7 = _LC2_C11;
-- Node name is '|LPM_ADD_SUB:113|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C8', type is buried
_LC3_C8 = LCELL( _EQ001);
_EQ001 = _LC6_C8 & _LC8_C8;
-- Node name is '|LPM_ADD_SUB:113|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C8', type is buried
_LC7_C8 = LCELL( _EQ002);
_EQ002 = _LC2_C8 & _LC6_C8 & _LC8_C8;
-- Node name is '|LPM_ADD_SUB:113|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C8', type is buried
_LC5_C8 = LCELL( _EQ003);
_EQ003 = _LC2_C8 & _LC4_C8 & _LC6_C8 & _LC8_C8;
-- Node name is '|LPM_ADD_SUB:113|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C2', type is buried
_LC7_C2 = LCELL( _EQ004);
_EQ004 = _LC5_C8 & _LC7_C11;
-- Node name is '|LPM_ADD_SUB:113|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C11', type is buried
_LC6_C11 = LCELL( _EQ005);
_EQ005 = _LC1_C11 & _LC5_C8 & _LC7_C11;
-- Node name is '|LPM_ADD_SUB:113|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C11', type is buried
_LC8_C11 = LCELL( _EQ006);
_EQ006 = _LC1_C11 & _LC5_C8 & _LC5_C11 & _LC7_C11;
-- Node name is ':3'
-- Equation name is '_LC2_C11', type is buried
_LC2_C11 = DFFE( _EQ007, GLOBAL( cP), VCC, VCC, VCC);
_EQ007 = _LC1_C8 & _LC2_C11 & !_LC8_C11
# _LC1_C8 & !_LC2_C11 & _LC8_C11
# _LC2_C11 & !LD;
-- Node name is ':5'
-- Equation name is '_LC5_C11', type is buried
_LC5_C11 = DFFE( _EQ008, GLOBAL( cP), VCC, VCC, VCC);
_EQ008 = _LC1_C8 & _LC5_C11 & !_LC6_C11
# _LC1_C8 & !_LC5_C11 & _LC6_C11
# _LC5_C11 & !LD;
-- Node name is ':7'
-- Equation name is '_LC1_C11', type is buried
_LC1_C11 = DFFE( _EQ009, GLOBAL( cP), VCC, VCC, VCC);
_EQ009 = _LC1_C8 & _LC1_C11 & !_LC7_C2
# _LC1_C8 & !_LC1_C11 & _LC7_C2
# _LC1_C11 & !LD;
-- Node name is ':9'
-- Equation name is '_LC7_C11', type is buried
_LC7_C11 = DFFE( _EQ010, GLOBAL( cP), VCC, VCC, VCC);
_EQ010 = _LC1_C8 & !_LC5_C8 & _LC7_C11
# _LC1_C8 & _LC5_C8 & !_LC7_C11
# _LC7_C11 & !LD;
-- Node name is ':11'
-- Equation name is '_LC4_C8', type is buried
_LC4_C8 = DFFE( _EQ011, GLOBAL( cP), VCC, VCC, VCC);
_EQ011 = _LC1_C8 & _LC4_C8 & !_LC7_C8
# _LC1_C8 & !_LC4_C8 & _LC7_C8
# _LC4_C8 & !LD;
-- Node name is ':13'
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = DFFE( _EQ012, GLOBAL( cP), VCC, VCC, VCC);
_EQ012 = _LC1_C8 & _LC2_C8 & !_LC3_C8
# _LC1_C8 & !_LC2_C8 & _LC3_C8
# _LC2_C8 & !LD;
-- Node name is ':15'
-- Equation name is '_LC6_C8', type is buried
_LC6_C8 = DFFE( _EQ013, GLOBAL( cP), VCC, VCC, VCC);
_EQ013 = _LC1_C8 & _LC6_C8 & !_LC8_C8
# _LC1_C8 & !_LC6_C8 & _LC8_C8
# _LC6_C8 & !LD;
-- Node name is ':17'
-- Equation name is '_LC8_C8', type is buried
_LC8_C8 = DFFE( _EQ014, GLOBAL( cP), VCC, VCC, VCC);
_EQ014 = _LC8_C8 & !LD
# !_LC8_C8 & LD;
-- Node name is '~55~1'
-- Equation name is '~55~1', location is LC4_C11, type is buried.
-- synthesized logic cell
_LC4_C11 = LCELL( _EQ015);
_EQ015 = _LC4_C8
# _LC2_C11
# _LC2_C8;
-- Node name is '~55~2'
-- Equation name is '~55~2', location is LC3_C11, type is buried.
-- synthesized logic cell
_LC3_C11 = LCELL( _EQ016);
_EQ016 = _LC7_C11
# _LC4_C11
# !_LC5_C11
# !_LC1_C11;
-- Node name is '~210~1'
-- Equation name is '~210~1', location is LC1_C8, type is buried.
-- synthesized logic cell
_LC1_C8 = LCELL( _EQ017);
_EQ017 = !_LC6_C8 & LD
# !_LC8_C8 & LD
# _LC3_C11 & LD;
Project Information f:\ss\ss\jishu.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 21,449K
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