📄 zongxianshi.rpt
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Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 231/1152 ( 20%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 4 8 8 8 8 8 8 8 8 8 8 0 3 0 8 8 0 8 0 0 2 0 8 6 135/0
B: 7 8 2 8 6 8 7 4 8 8 0 8 0 1 0 0 0 0 0 0 0 0 0 0 0 75/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 6 0 0 8 0 0 0 4 0 0 8 34/0
D: 0 8 0 8 8 8 8 0 0 0 8 0 0 0 8 2 3 2 0 8 8 8 0 8 8 103/0
E: 8 8 8 8 8 8 8 8 8 3 8 8 0 8 8 6 7 8 8 8 8 7 7 8 8 182/0
F: 8 0 8 8 8 8 8 4 6 0 4 8 0 0 7 0 0 8 8 0 0 0 0 8 2 103/0
Total: 31 28 26 40 38 40 39 24 30 19 28 32 0 20 29 16 18 26 24 16 16 21 7 32 32 632/0
Device-Specific Information: d:\shiyan\ss\ss\zongxianshi.rpt
zongxianshi
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
125 - - - -- INPUT G 0 0 0 0 CLK
55 - - - -- INPUT G 0 0 0 0 CP
124 - - - -- INPUT 0 0 0 8 LD
54 - - - -- INPUT G 0 0 0 0 SCANCLK
56 - - - -- INPUT G 0 0 0 10 START
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\shiyan\ss\ss\zongxianshi.rpt
zongxianshi
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
28 - - E -- OUTPUT 0 1 0 0 getdata0
87 - - E -- OUTPUT 0 1 0 0 getdata1
117 - - - 05 OUTPUT 0 1 0 0 getdata2
136 - - - 20 OUTPUT 0 1 0 0 getdata3
27 - - E -- OUTPUT 0 1 0 0 getdata4
82 - - E -- OUTPUT 0 1 0 0 getdata5
14 - - C -- OUTPUT 0 1 0 0 getdata6
30 - - F -- OUTPUT 0 1 0 0 getdata7
137 - - - 20 OUTPUT 0 1 0 0 jishudata0
38 - - - 22 OUTPUT 0 1 0 0 jishudata1
7 - - A -- OUTPUT 0 1 0 0 jishudata2
138 - - - 21 OUTPUT 0 1 0 0 jishudata3
47 - - - 16 OUTPUT 0 1 0 0 jishudata4
48 - - - 15 OUTPUT 0 1 0 0 jishudata5
19 - - D -- OUTPUT 0 1 0 0 jishudata6
33 - - F -- OUTPUT 0 1 0 0 jishudata7
22 - - D -- OUTPUT 0 1 0 0 pause
23 - - D -- OUTPUT 0 1 0 0 rev
21 - - D -- OUTPUT 0 1 0 0 run
13 - - C -- OUTPUT 0 1 0 0 segout0
92 - - C -- OUTPUT 0 1 0 0 segout1
89 - - C -- OUTPUT 0 1 0 0 segout2
91 - - C -- OUTPUT 0 1 0 0 segout3
12 - - C -- OUTPUT 0 1 0 0 segout4
90 - - C -- OUTPUT 0 1 0 0 segout5
11 - - C -- OUTPUT 0 1 0 0 segout6
122 - - - 13 OUTPUT 0 1 0 0 selout0
26 - - E -- OUTPUT 0 1 0 0 selout1
31 - - F -- OUTPUT 0 1 0 0 selout2
32 - - F -- OUTPUT 0 1 0 0 selout3
17 - - D -- OUTPUT 0 1 0 0 tJ
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\shiyan\ss\ss\zongxianshi.rpt
zongxianshi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - D 07 OR2 0 2 0 3 |couter:u1|LPM_ADD_SUB:225|addcore:adder|pcarry1
- 1 - D 07 OR2 0 3 0 8 |couter:u1|LPM_ADD_SUB:225|addcore:adder|pcarry3
- 4 - E 02 OR2 0 2 0 7 |couter:u1|LPM_ADD_SUB:225|addcore:adder|pcarry4
- 1 - E 11 OR2 0 3 0 3 |couter:u1|LPM_ADD_SUB:225|addcore:adder|pcarry6
- 6 - D 11 AND2 0 2 0 2 |couter:u1|LPM_ADD_SUB:368|addcore:adder|:75
- 1 - D 11 AND2 0 2 0 5 |couter:u1|LPM_ADD_SUB:368|addcore:adder|:79
- 8 - D 11 AND2 0 2 0 1 |couter:u1|LPM_ADD_SUB:368|addcore:adder|:83
- 6 - D 02 AND2 0 3 0 1 |couter:u1|LPM_ADD_SUB:368|addcore:adder|:87
- 1 - D 02 AND2 0 4 0 2 |couter:u1|LPM_ADD_SUB:368|addcore:adder|:91
- 4 - D 02 AND2 0 2 0 1 |couter:u1|LPM_ADD_SUB:368|addcore:adder|:95
- 1 - D 24 DFFE + 1 1 1 1 |couter:u1|:19
- 5 - E 11 DFFE + 0 2 0 8 |couter:u1|linshi17 (|couter:u1|:21)
- 1 - E 02 DFFE + 0 3 0 7 |couter:u1|linshi16 (|couter:u1|:22)
- 2 - A 04 DFFE + 0 3 0 48 |couter:u1|linshi15 (|couter:u1|:23)
- 7 - F 07 DFFE + 0 3 0 62 |couter:u1|linshi14 (|couter:u1|:24)
- 4 - D 07 DFFE + 0 3 0 23 |couter:u1|linshi13 (|couter:u1|:25)
- 2 - D 07 DFFE + 0 3 0 24 |couter:u1|linshi12 (|couter:u1|:26)
- 3 - D 07 DFFE + 0 3 0 14 |couter:u1|linshi11 (|couter:u1|:27)
- 1 - E 07 DFFE + 0 3 0 12 |couter:u1|linshi10 (|couter:u1|:28)
- 5 - D 02 DFFE + 1 2 0 1 |couter:u1|linshi27 (|couter:u1|:29)
- 3 - D 02 DFFE + 1 2 0 2 |couter:u1|linshi26 (|couter:u1|:30)
- 7 - D 02 DFFE + 1 2 0 2 |couter:u1|linshi25 (|couter:u1|:31)
- 2 - D 11 DFFE + 1 2 0 3 |couter:u1|linshi24 (|couter:u1|:32)
- 3 - D 11 DFFE + 1 2 0 4 |couter:u1|linshi23 (|couter:u1|:33)
- 7 - D 11 DFFE + 1 2 0 1 |couter:u1|linshi22 (|couter:u1|:34)
- 5 - D 11 DFFE + 1 2 0 1 |couter:u1|linshi21 (|couter:u1|:35)
- 4 - D 11 DFFE + 1 1 0 2 |couter:u1|linshi20 (|couter:u1|:36)
- 8 - E 11 OR2 ! 0 2 0 18 |couter:u1|:122
- 8 - D 02 OR2 s ! 0 3 0 1 |couter:u1|~175~1
- 2 - D 02 OR2 ! 0 4 0 8 |couter:u1|:175
- 5 - E 02 OR2 0 4 0 1 |couter:u1|:321
- 7 - A 04 OR2 0 3 0 1 |couter:u1|:327
- 1 - F 07 OR2 0 3 0 1 |couter:u1|:333
- 8 - D 07 OR2 0 4 0 1 |couter:u1|:339
- 7 - D 07 OR2 0 3 0 1 |couter:u1|:345
- 6 - D 07 OR2 0 3 0 1 |couter:u1|:351
- 3 - E 11 OR2 0 4 0 1 |couter:u1|:460
- 7 - D 05 AND2 0 2 0 10 |JISHU:u0|LPM_ADD_SUB:113|addcore:adder|:75
- 2 - D 04 AND2 0 2 0 12 |JISHU:u0|LPM_ADD_SUB:113|addcore:adder|:79
- 1 - D 04 AND2 0 2 0 8 |JISHU:u0|LPM_ADD_SUB:113|addcore:adder|:83
- 2 - B 07 AND2 0 2 0 5 |JISHU:u0|LPM_ADD_SUB:113|addcore:adder|:87
- 8 - A 04 AND2 0 2 0 1 |JISHU:u0|LPM_ADD_SUB:113|addcore:adder|:91
- 6 - A 04 AND2 0 3 0 1 |JISHU:u0|LPM_ADD_SUB:113|addcore:adder|:95
- 3 - A 04 DFFE + 1 2 0 6 |JISHU:u0|:3
- 1 - A 04 DFFE + 1 2 0 40 |JISHU:u0|:5
- 5 - A 04 DFFE + 1 2 0 8 |JISHU:u0|:7
- 3 - A 08 DFFE + 1 2 0 28 |JISHU:u0|:9
- 2 - A 08 DFFE + 1 2 0 22 |JISHU:u0|:11
- 1 - A 08 DFFE + 1 2 0 42 |JISHU:u0|:13
- 5 - A 08 DFFE + 1 2 0 21 |JISHU:u0|:15
- 6 - A 08 DFFE + 1 0 0 11 |JISHU:u0|:17
- 8 - A 08 OR2 ! 0 2 0 8 |JISHU:u0|:55
- 3 - F 14 DFFE + 0 3 0 4 |sevenduan:u4|q2 (|sevenduan:u4|:72)
- 6 - F 14 DFFE + 0 2 0 5 |sevenduan:u4|q1 (|sevenduan:u4|:73)
- 7 - F 14 DFFE + 0 0 0 6 |sevenduan:u4|q0 (|sevenduan:u4|:74)
- 5 - F 14 OR2 ! 0 3 1 2 |sevenduan:u4|:108
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