📄 zongxianshi.rpt
字号:
selout1 | 26 83 | RESERVED
getdata4 | 27 82 | getdata5
getdata0 | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
getdata7 | 30 79 | RESERVED
selout2 | 31 78 | RESERVED
selout3 | 32 77 | ^MSEL0
jishudata7 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R j R G R R R R V R j j R G R V V S C S G G R R V R R R R G R R R R V R
E i E N E E E E C E i i E N E C C C P T N N E E C E E E E N E E E E C E
S s S D S S S S C S s s S D S C C A A D D S S C S S S S D S S S S C S
E h E I E E E E I E h h E I E I I N R I I E E I E E E E I E E E E I E
R u R O R R R R O R u u R O R N N C T N N R R O R R R R O R R R R O R
V d V V V V V V d d V V T T L T T V V V V V V V V V V V
E a E E E E E E a a E E K E E E E E E E E E E E
D t D D D D D D t t D D D D D D D D D D D D D
a a a
1 4 5
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\shiyan\ss\ss\zongxianshi.rpt
zongxianshi
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 17/22( 77%)
A2 4/ 8( 50%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
A3 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 13/22( 59%)
A4 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 2/2 1/2 6/22( 27%)
A5 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 8/22( 36%)
A6 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 14/22( 63%)
A7 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 15/22( 68%)
A8 8/ 8(100%) 5/ 8( 62%) 8/ 8(100%) 1/2 0/2 6/22( 27%)
A9 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
A10 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
A11 8/ 8(100%) 1/ 8( 12%) 8/ 8(100%) 0/2 0/2 10/22( 45%)
A12 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 13/22( 59%)
A13 3/ 8( 37%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
A15 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 16/22( 72%)
A16 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 13/22( 59%)
A18 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
A21 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
A23 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
A24 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
B1 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
B2 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 17/22( 77%)
B3 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
B4 8/ 8(100%) 4/ 8( 50%) 7/ 8( 87%) 0/2 0/2 6/22( 27%)
B5 6/ 8( 75%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
B6 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
B7 7/ 8( 87%) 4/ 8( 50%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
B8 4/ 8( 50%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 9/22( 40%)
B9 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
B10 8/ 8(100%) 7/ 8( 87%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
B12 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
B13 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C13 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
C14 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
C17 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 4/22( 18%)
C21 4/ 8( 50%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
C24 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
D2 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
D4 8/ 8(100%) 3/ 8( 37%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
D5 8/ 8(100%) 5/ 8( 62%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
D6 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
D7 8/ 8(100%) 4/ 8( 50%) 0/ 8( 0%) 1/2 1/2 6/22( 27%)
D11 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 2/22( 9%)
D14 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
D15 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
D16 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 3/22( 13%)
D17 2/ 8( 25%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
D19 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 11/22( 50%)
D20 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
D21 8/ 8(100%) 4/ 8( 50%) 0/ 8( 0%) 0/2 0/2 15/22( 68%)
D23 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 3/22( 13%)
D24 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 3/22( 13%)
E1 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 11/22( 50%)
E2 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 13/22( 59%)
E3 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
E4 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
E5 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
E6 8/ 8(100%) 5/ 8( 62%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
E7 8/ 8(100%) 4/ 8( 50%) 7/ 8( 87%) 1/2 1/2 10/22( 45%)
E8 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 11/22( 50%)
E9 8/ 8(100%) 1/ 8( 12%) 8/ 8(100%) 0/2 0/2 11/22( 50%)
E10 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
E11 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 11/22( 50%)
E12 8/ 8(100%) 3/ 8( 37%) 7/ 8( 87%) 0/2 0/2 7/22( 31%)
E13 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 10/22( 45%)
E14 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 16/22( 72%)
E15 6/ 8( 75%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 8/22( 36%)
E16 7/ 8( 87%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 6/22( 27%)
E17 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 14/22( 63%)
E18 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
E19 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
E20 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
E21 7/ 8( 87%) 2/ 8( 25%) 6/ 8( 75%) 0/2 0/2 11/22( 50%)
E22 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
E23 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
E24 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
F1 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
F3 8/ 8(100%) 3/ 8( 37%) 8/ 8(100%) 0/2 0/2 8/22( 36%)
F4 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
F5 8/ 8(100%) 5/ 8( 62%) 6/ 8( 75%) 0/2 0/2 5/22( 22%)
F6 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 15/22( 68%)
F7 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 12/22( 54%)
F8 4/ 8( 50%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
F9 6/ 8( 75%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
F11 4/ 8( 50%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
F12 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 16/22( 72%)
F14 7/ 8( 87%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 0/22( 0%)
F17 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
F18 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 15/22( 68%)
F23 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 15/22( 68%)
F24 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 5/6 ( 83%)
Total I/O pins used: 31/96 ( 32%)
Total logic cells used: 632/1152 ( 54%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.43/4 ( 85%)
Total fan-in: 2172/4608 ( 47%)
Total input pins required: 5
Total input I/O cell registers required: 0
Total output pins required: 31
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 632
Total flipflops required: 37
Total packed registers required: 0
Total logic cells in carry chains: 0
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