📄 sevenduan.rpt
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- 7 - C 21 OR2 ! 0 4 0 1 :7803
- 5 - C 14 OR2 s 0 3 0 3 ~7820~1
- 6 - C 14 OR2 s 0 3 0 3 ~7820~2
- 8 - C 21 OR2 ! 0 4 0 1 :7821
- 2 - C 21 OR2 ! 0 4 0 1 :7832
- 1 - C 19 OR2 s 0 3 0 2 ~7850~1
- 2 - C 13 OR2 s 0 3 0 1 ~7850~2
- 5 - C 20 OR2 ! 0 4 0 1 :7851
- 2 - C 20 OR2 ! 0 4 0 1 :7862
- 7 - C 18 OR2 s 0 3 0 2 ~7880~1
- 3 - C 15 OR2 s 0 3 0 1 ~7880~2
- 3 - C 03 OR2 ! 0 4 0 1 :7880
- 4 - C 03 OR2 ! 1 3 0 1 :7892
- 8 - C 08 OR2 s 2 2 0 2 ~7910~1
- 6 - C 02 OR2 s 0 3 0 3 ~7910~2
- 2 - C 03 OR2 ! 0 4 0 1 :7910
- 6 - C 11 OR2 ! 0 3 0 1 :7922
- 5 - C 10 OR2 s 0 3 0 3 ~7940~1
- 3 - C 10 OR2 s 2 2 0 4 ~7940~2
- 7 - C 11 OR2 ! 0 4 0 1 :7940
- 1 - C 11 OR2 ! 0 4 0 1 :7953
- 1 - C 02 OR2 s 2 2 0 3 ~7970~1
- 3 - C 07 OR2 s 2 2 0 5 ~7970~2
- 1 - C 09 OR2 ! 0 4 0 1 :7971
- 7 - C 12 OR2 s 0 3 0 4 ~8000~1
- 5 - C 09 OR2 s ! 0 3 0 1 ~8000~2
- 7 - C 09 OR2 ! 0 4 0 1 :8000
- 4 - B 14 OR2 ! 0 4 0 1 :8001
- 1 - B 14 OR2 ! 0 4 0 1 :8012
- 3 - C 22 OR2 s 0 3 0 4 ~8030~1
- 6 - B 22 OR2 ! 0 4 0 1 :8031
- 7 - B 22 OR2 ! 0 4 0 1 :8042
- 5 - B 19 OR2 s 0 2 0 1 ~8060~1
- 2 - B 22 OR2 ! 0 4 0 1 :8061
- 8 - B 13 OR2 ! 0 4 0 1 :8073
- 5 - B 13 OR2 ! 0 4 1 1 :8081
- 3 - C 14 AND2 1 1 0 1 :8099
- 4 - C 14 OR2 0 4 0 1 :8105
- 7 - C 14 OR2 0 4 0 1 :8111
- 8 - C 14 OR2 0 4 0 1 :8117
- 1 - C 14 OR2 0 4 0 1 :8123
- 4 - C 15 OR2 0 4 0 1 :8129
- 5 - C 15 OR2 0 4 0 1 :8135
- 6 - C 15 OR2 0 4 0 1 :8141
- 7 - C 15 OR2 0 4 0 1 :8147
- 8 - C 15 OR2 0 4 0 1 :8153
- 1 - C 15 OR2 0 4 0 1 :8159
- 1 - C 18 OR2 0 4 0 1 :8165
- 4 - C 18 OR2 0 3 0 1 :8171
- 5 - C 18 OR2 0 4 0 1 :8177
- 6 - C 18 OR2 0 4 0 1 :8183
- 1 - C 03 OR2 0 3 0 1 :8195
- 4 - C 08 OR2 2 2 0 1 :8199
- 3 - C 08 OR2 0 4 0 1 :8201
- 5 - C 08 OR2 2 2 0 1 :8207
- 7 - C 08 OR2 2 2 0 1 :8211
- 6 - C 08 OR2 0 4 0 1 :8213
- 2 - C 08 OR2 2 2 0 1 :8219
- 8 - C 07 OR2 2 2 0 1 :8223
- 7 - C 07 OR2 0 4 0 1 :8225
- 1 - C 07 OR2 2 2 0 1 :8231
- 7 - C 10 OR2 2 2 0 1 :8235
- 6 - C 10 OR2 0 4 0 1 :8237
- 1 - C 10 OR2 2 2 0 1 :8241
- 8 - C 10 OR2 2 2 0 1 :8243
- 3 - C 01 OR2 2 2 0 1 :8247
- 2 - C 01 OR2 2 2 0 1 :8249
- 5 - C 01 OR2 2 2 0 1 :8253
- 4 - C 01 OR2 2 2 0 1 :8255
- 7 - C 01 OR2 2 2 0 1 :8259
- 6 - C 01 OR2 2 2 0 1 :8261
- 1 - C 01 OR2 2 2 0 1 :8265
- 8 - C 01 OR2 2 2 0 1 :8267
- 3 - C 04 OR2 2 2 0 1 :8271
- 2 - C 04 OR2 2 2 0 1 :8273
- 5 - C 04 OR2 2 2 0 1 :8277
- 4 - C 04 OR2 2 2 0 1 :8279
- 7 - C 04 OR2 2 2 0 1 :8283
- 6 - C 04 OR2 2 2 0 1 :8285
- 8 - C 04 OR2 2 2 0 1 :8291
- 1 - C 04 OR2 0 4 0 1 :8297
- 1 - B 21 OR2 0 4 0 1 :8303
- 2 - B 21 OR2 0 4 0 1 :8309
- 3 - B 21 OR2 0 4 0 1 :8315
- 4 - B 21 OR2 0 4 0 1 :8321
- 5 - B 21 OR2 0 4 0 1 :8327
- 6 - B 21 OR2 0 4 0 1 :8333
- 7 - B 21 OR2 0 4 0 1 :8339
- 8 - B 21 OR2 0 4 0 1 :8345
- 4 - B 19 OR2 0 4 0 1 :8351
- 7 - B 19 OR2 0 4 0 1 :8355
- 3 - B 19 OR2 0 4 0 1 :8361
- 3 - B 13 OR2 0 4 0 1 :8375
- 6 - B 13 OR2 0 4 0 1 :8381
- 4 - B 13 OR2 0 4 1 1 :8384
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\ss\sevenduan.rpt
sevenduan
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 71/ 96( 73%) 38/ 48( 79%) 24/ 48( 50%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 31/ 96( 32%) 28/ 48( 58%) 28/ 48( 58%) 3/16( 18%) 3/16( 18%) 0/16( 0%)
C: 48/ 96( 50%) 31/ 48( 64%) 31/ 48( 64%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 7/24( 29%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 8/24( 33%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 6/24( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\ss\sevenduan.rpt
sevenduan
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 SCANCLK
Device-Specific Information: d:\ss\sevenduan.rpt
sevenduan
** EQUATIONS **
BIN0 : INPUT;
BIN1 : INPUT;
BIN2 : INPUT;
BIN3 : INPUT;
BIN4 : INPUT;
BIN5 : INPUT;
BIN6 : INPUT;
BIN7 : INPUT;
SCANCLK : INPUT;
time0 : INPUT;
time1 : INPUT;
time2 : INPUT;
time3 : INPUT;
time4 : INPUT;
time5 : INPUT;
time6 : INPUT;
time7 : INPUT;
-- Node name is 'getdata0'
-- Equation name is 'getdata0', type is output
getdata0 = _LC4_A23;
-- Node name is 'getdata1'
-- Equation name is 'get⌨️ 快捷键说明
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