📄 sevenduan.rpt
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B13 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
B14 5/ 8( 62%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
B16 7/ 8( 87%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 0/22( 0%)
B19 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
B20 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 15/22( 68%)
B21 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 12/22( 54%)
B22 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 13/22( 59%)
C1 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 8/22( 36%)
C2 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 9/22( 40%)
C3 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 16/22( 72%)
C4 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 10/22( 45%)
C5 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 7/22( 31%)
C6 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
C7 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
C8 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
C9 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 13/22( 59%)
C10 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
C11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
C12 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
C13 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
C14 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
C15 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
C16 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
C17 7/ 8( 87%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
C18 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
C19 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 13/22( 59%)
C20 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
C21 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
C22 7/ 8( 87%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 13/22( 59%)
C23 8/ 8(100%) 8/ 8(100%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
C24 8/ 8(100%) 4/ 8( 50%) 7/ 8( 87%) 0/2 0/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 38/53 ( 71%)
Total logic cells used: 505/576 ( 87%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.48/4 ( 87%)
Total fan-in: 1762/2304 ( 76%)
Total input pins required: 17
Total input I/O cell registers required: 0
Total output pins required: 27
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 505
Total flipflops required: 3
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 222/ 576 ( 38%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 8 8 7 8 8 8 8 8 8 8 8 0 8 7 8 8 8 8 8 7 8 8 8 8 189/0
B: 0 7 8 8 8 8 8 5 8 7 8 8 0 8 5 0 7 0 0 8 8 8 8 0 0 135/0
C: 8 8 8 8 8 8 8 8 8 8 8 3 0 6 8 8 8 7 8 8 6 8 7 8 8 181/0
Total: 16 23 24 23 24 24 24 21 24 23 24 19 0 22 20 16 23 15 16 24 21 24 23 16 16 505/0
Device-Specific Information: d:\ss\sevenduan.rpt
sevenduan
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
22 - - B -- INPUT 0 0 0 5 BIN0
2 - - - -- INPUT 0 0 0 61 BIN1
43 - - - -- INPUT 0 0 0 17 BIN2
9 - - - 02 INPUT 0 0 0 17 BIN3
44 - - - -- INPUT 0 0 0 57 BIN4
21 - - B -- INPUT 0 0 0 5 BIN5
38 - - - 10 INPUT 0 0 0 11 BIN6
66 - - B -- INPUT 0 0 0 5 BIN7
1 - - - -- INPUT G 0 0 0 0 SCANCLK
30 - - C -- INPUT 0 0 0 7 time0
42 - - - -- INPUT 0 0 0 47 time1
59 - - C -- INPUT 0 0 0 17 time2
58 - - C -- INPUT 0 0 0 17 time3
84 - - - -- INPUT 0 0 0 44 time4
27 - - C -- INPUT 0 0 0 7 time5
28 - - C -- INPUT 0 0 0 11 time6
29 - - C -- INPUT 0 0 0 7 time7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\ss\sevenduan.rpt
sevenduan
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
78 - - - 24 OUTPUT 0 1 0 0 getdata0
73 - - A -- OUTPUT 0 1 0 0 getdata1
18 - - A -- OUTPUT 0 1 0 0 getdata2
69 - - A -- OUTPUT 0 1 0 0 getdata3
16 - - A -- OUTPUT 0 1 0 0 getdata4
19 - - A -- OUTPUT 0 1 0 0 getdata5
36 - - - 07 OUTPUT 0 1 0 0 getdata6
17 - - A -- OUTPUT 0 1 0 0 getdata7
47 - - - 14 OUTPUT 0 1 0 0 jishudata0
83 - - - 13 OUTPUT 0 1 0 0 jishudata1
62 - - C -- OUTPUT 0 1 0 0 jishudata2
65 - - B -- OUTPUT 0 1 0 0 jishudata3
37 - - - 09 OUTPUT 0 1 0 0 jishudata4
49 - - - 16 OUTPUT 0 1 0 0 jishudata5
60 - - C -- OUTPUT 0 1 0 0 jishudata6
51 - - - 18 OUTPUT 0 1 0 0 jishudata7
52 - - - 19 OUTPUT 0 1 0 0 SEGOUT0
54 - - - 21 OUTPUT 0 1 0 0 SEGOUT1
71 - - A -- OUTPUT 0 1 0 0 SEGOUT2
70 - - A -- OUTPUT 0 1 0 0 SEGOUT3
53 - - - 20 OUTPUT 0 1 0 0 SEGOUT4
72 - - A -- OUTPUT 0 1 0 0 SEGOUT5
81 - - - 22 OUTPUT 0 1 0 0 SEGOUT6
48 - - - 15 OUTPUT 0 1 0 0 SELOUT0
64 - - B -- OUTPUT 0 1 0 0 SELOUT1
61 - - C -- OUTPUT 0 1 0 0 SELOUT2
67 - - B -- OUTPUT 0 1 0 0 SELOUT3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\ss\sevenduan.rpt
sevenduan
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 16 DFFE + 0 3 0 4 q2 (:72)
- 5 - B 16 DFFE + 0 2 0 5 q1 (:73)
- 6 - B 16 DFFE + 0 0 0 6 q0 (:74)
- 1 - B 16 OR2 ! 0 3 1 2 :108
- 3 - B 16 OR2 ! 0 3 1 4 :355
- 7 - B 16 OR2 ! 0 3 1 4 :359
- 2 - B 16 OR2 ! 0 3 1 4 :363
- 5 - A 18 OR2 0 3 0 1 :376
- 6 - A 18 OR2 0 3 0 1 :382
- 3 - A 18 OR2 0 3 0 19 :388
- 7 - C 17 OR2 0 4 0 1 :394
- 7 - A 08 OR2 0 4 0 1 :397
- 1 - A 08 OR2 0 3 0 19 :400
- 2 - A 14 OR2 0 3 0 1 :406
- 4 - A 18 OR2 0 3 0 1 :409
- 2 - A 18 OR2 0 3 0 18 :412
- 7 - A 23 OR2 0 3 0 1 :418
- 8 - A 23 OR2 0 3 0 1 :421
- 2 - A 23 OR2 0 3 0 18 :424
- 4 - A 19 AND2 0 4 0 4 :443
- 8 - A 19 OR2 ! 0 4 0 4 :448
- 6 - A 19 AND2 s 0 2 0 1 ~453~1
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