zong.vhd

自己 写的课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;

library Altera;
use Altera.maxplus2.all;


entity zong is
port(LD:IN std_logic;
CLK:IN STD_LOGIC;
CP:IN std_logic;
START:IN std_logic;
SJXSH:OUT integer range 0 to 255;
tJ:BUFFER std_logic;
run:out std_logic;
rev:out std_logic;
pause:out std_logic
);
end zong; 

architecture rtl of zong is
signal y0:integer range 0 to 255;
signal y1:std_logic_vector(2 downto 0);
signal clkout_1,clkout_2,g0,g1,g2:std_logic;

component couter
port(start:IN std_logic;
     clk:IN std_logic;
     CHUSHItime:IN integer range 0 to 255;
     SJXSH:OUT integer range 0 to 255;
     tJ:BUFFER std_logic);
     end component; 

component JISHU
port(LD:IN std_logic;
cP:IN std_logic;
JISHUtime:BUFFER integer range 0 to 255);
end component; 

component SHIXU
port(clk:in std_logic;
TG:in std_logic;
start:in std_logic;
SHUCHU:BUFFER std_logic_VECTOR(2 DOWNTO 0)
);
end component;


component YIMA
port(run:out std_logic;
rev:out std_logic;
pause:out std_logic;
SHURU:IN std_logic_VECTOR(2 DOWNTO 0)
);
end component;
begin
 u0:JiSHU  port map(LD,CP,y0);
 u1:couter  port map(start,clk,y0,SJXSH,tj);
 u2:SHIXU  port map(clk,TJ,start,y1);
 u3:yima port map(run,rev,pause,y1);
 end rtl;