counter.vhd

自己 写的课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
entity counter is
port(start:IN std_logic;
clk:IN std_logic;
CHUSHItime:IN integer range 0 to 255;
SJXSH:OUT integer range 0 to 255;
tJ:BUFFER std_logic);
end counter; 
architecture behav of counter is
signal linshi1:integer range 0 to 255;
signal linshi2:integer range 0 to 31;

begin
process(clk,CHUSHItime)
begin
if(start='0')then linshi1<=CHUSHItime;
ELSIF(CLK'EVENT AND CLK='1')THEN
  if(linshi1=0)then 
   tJ<='1';
  ELSE
   IF(linshi2=30)then 
       linshi2<=0;
linshi1<=linshi1-1;
END IF;
   linshi2<=linshi2+1;

  END IF;
  END IF;
end process;
SJXSH<=linshi1;
end behav;