📄 shixu.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\shiyan\ss\ss\shixu.rpt
shixu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\shiyan\ss\ss\shixu.rpt
shixu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information: d:\shiyan\ss\ss\shixu.rpt
shixu
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 9 :45
Device-Specific Information: d:\shiyan\ss\ss\shixu.rpt
shixu
** EQUATIONS **
clk : INPUT;
start : INPUT;
TG : INPUT;
-- Node name is ':15' = 'QQ0'
-- Equation name is 'QQ0', location is LC5_A4, type is buried.
QQ0 = DFFE(!QQ0, GLOBAL( clk), VCC, VCC, !_LC1_A2);
-- Node name is ':14' = 'QQ1'
-- Equation name is 'QQ1', location is LC4_A4, type is buried.
QQ1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, !_LC1_A2);
_EQ001 = !_LC8_A4 & QQ0 & !QQ1
# !_LC8_A4 & !QQ0 & QQ1;
-- Node name is ':13' = 'QQ2'
-- Equation name is 'QQ2', location is LC6_A4, type is buried.
QQ2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, !_LC1_A2);
_EQ002 = !_LC2_A4 & !_LC8_A4 & QQ2
# _LC2_A4 & !_LC8_A4 & !QQ2;
-- Node name is ':12' = 'QQ3'
-- Equation name is 'QQ3', location is LC3_A4, type is buried.
QQ3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, !_LC1_A2);
_EQ003 = !_LC1_A4 & !_LC8_A4 & QQ3
# _LC1_A4 & !_LC8_A4 & !QQ3;
-- Node name is ':11' = 'QQ4'
-- Equation name is 'QQ4', location is LC7_A2, type is buried.
QQ4 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, !_LC1_A2);
_EQ004 = !_LC4_A2 & !_LC8_A4 & QQ4
# _LC4_A2 & !_LC8_A4 & !QQ4;
-- Node name is ':10' = 'QQ5'
-- Equation name is 'QQ5', location is LC7_A4, type is buried.
QQ5 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, !_LC1_A2);
_EQ005 = !_LC3_A2 & !_LC8_A4 & QQ5
# _LC3_A2 & !_LC8_A4 & !QQ5;
-- Node name is 'SHUCHU0'
-- Equation name is 'SHUCHU0', type is output
SHUCHU0 = _LC5_A2;
-- Node name is 'SHUCHU1'
-- Equation name is 'SHUCHU1', type is output
SHUCHU1 = _LC6_A2;
-- Node name is 'SHUCHU2'
-- Equation name is 'SHUCHU2', type is output
SHUCHU2 = _LC2_A2;
-- Node name is '|LPM_ADD_SUB:162|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = LCELL( _EQ006);
_EQ006 = QQ0 & QQ1;
-- Node name is '|LPM_ADD_SUB:162|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = LCELL( _EQ007);
_EQ007 = _LC2_A4 & QQ2;
-- Node name is '|LPM_ADD_SUB:162|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = LCELL( _EQ008);
_EQ008 = _LC1_A4 & QQ3;
-- Node name is '|LPM_ADD_SUB:162|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = LCELL( _EQ009);
_EQ009 = _LC1_A4 & QQ3 & QQ4;
-- Node name is ':4'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = DFFE( _EQ010, GLOBAL( clk), !_LC1_A2, VCC, VCC);
_EQ010 = !_LC2_A2 & _LC5_A2 & _LC6_A2 & _LC8_A4
# _LC2_A2 & !_LC6_A2
# _LC2_A2 & !_LC8_A4;
-- Node name is ':6'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = DFFE( _EQ011, GLOBAL( clk), !_LC1_A2, VCC, VCC);
_EQ011 = _LC6_A2 & !_LC8_A4
# !_LC2_A2 & !_LC5_A2 & _LC6_A2
# _LC5_A2 & !_LC6_A2 & _LC8_A4;
-- Node name is ':8'
-- Equation name is '_LC5_A2', type is buried
_LC5_A2 = DFFE( _EQ012, GLOBAL( clk), !_LC1_A2, VCC, VCC);
_EQ012 = _LC5_A2 & !_LC8_A4
# !_LC5_A2 & _LC8_A4;
-- Node name is ':45'
-- Equation name is '_LC1_A2', type is buried
!_LC1_A2 = _LC1_A2~NOT;
_LC1_A2~NOT = LCELL( _EQ013);
_EQ013 = start & !TG;
-- Node name is ':65'
-- Equation name is '_LC8_A4', type is buried
!_LC8_A4 = _LC8_A4~NOT;
_LC8_A4~NOT = LCELL( _EQ014);
_EQ014 = QQ3
# QQ4
# !QQ5
# !_LC1_A4;
Project Information d:\shiyan\ss\ss\shixu.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,816K
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