📄 zuizhongxyjgdf.rpt
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E21 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 10/22( 45%)
E22 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
E23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
E24 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
F1 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 13/22( 59%)
F2 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
F4 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
F5 2/ 8( 25%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 2/22( 9%)
F6 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F8 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
F9 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 11/22( 50%)
F10 8/ 8(100%) 6/ 8( 75%) 6/ 8( 75%) 0/2 0/2 5/22( 22%)
F11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
F12 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
F13 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
F14 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
F15 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 13/22( 59%)
F16 8/ 8(100%) 5/ 8( 62%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
F17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
F18 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
F23 6/ 8( 75%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
F24 8/ 8(100%) 6/ 8( 75%) 7/ 8( 87%) 1/2 0/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 35/96 ( 36%)
Total logic cells used: 628/1152 ( 54%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.38/4 ( 84%)
Total fan-in: 2123/4608 ( 46%)
Total input pins required: 5
Total input I/O cell registers required: 0
Total output pins required: 31
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 628
Total flipflops required: 37
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 231/1152 ( 20%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 3 0 0 0 0 0 0 0 8 0 5 0 8 8 0 3 0 0 0 0 35/0
B: 0 0 0 0 0 0 0 8 0 0 8 0 0 7 7 0 2 0 0 0 0 8 2 8 0 50/0
C: 7 8 8 4 8 0 8 0 8 0 0 3 0 8 3 3 8 0 1 7 8 8 8 8 1 117/0
D: 8 7 8 8 8 7 8 3 8 0 8 8 0 8 2 3 8 8 6 2 7 4 1 8 4 142/0
E: 8 2 8 6 2 8 8 8 8 8 8 7 0 8 8 8 5 8 5 8 0 8 8 1 8 156/0
F: 8 7 0 8 2 8 0 6 8 8 8 8 0 8 8 8 8 8 3 0 0 0 0 6 8 128/0
Total: 31 24 24 26 20 26 24 25 32 16 32 26 0 47 28 27 31 32 23 17 18 28 19 31 21 628/0
Device-Specific Information: f:\ss\ss\zuizhongxyjgdf.rpt
zuizhongxyjgdf
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
128 - - - 13 INPUT 0 0 0 26 clk
122 - - - 13 INPUT 0 0 0 8 CP
72 - - - 03 INPUT 0 0 0 9 Ld
125 - - - -- INPUT G 0 0 0 0 SACNCLK
73 - - - 01 INPUT 0 0 0 18 START
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\ss\ss\zuizhongxyjgdf.rpt
zuizhongxyjgdf
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
14 - - C -- OUTPUT 0 1 0 0 GETDATA0
143 - - A -- OUTPUT 0 1 0 0 GETDATA1
7 - - A -- OUTPUT 0 1 0 0 GETDATA2
65 - - - 09 OUTPUT 0 1 0 0 GETDATA3
91 - - C -- OUTPUT 0 1 0 0 GETDATA4
100 - - A -- OUTPUT 0 1 0 0 GETDATA5
68 - - - 07 OUTPUT 0 1 0 0 GETDATA6
109 - - A -- OUTPUT 0 1 0 0 GETDATA7
12 - - C -- OUTPUT 0 1 0 0 JISHUDATA0
144 - - A -- OUTPUT 0 1 0 0 JISHUDATA1
42 - - - 19 OUTPUT 0 1 0 0 JISHUDATA2
101 - - A -- OUTPUT 0 1 0 0 JISHUDATA3
140 - - - 22 OUTPUT 0 1 0 0 JISHUDATA4
138 - - - 21 OUTPUT 0 1 0 0 JISHUDATA5
63 - - - 10 OUTPUT 0 1 0 0 JISHUDATA6
64 - - - 09 OUTPUT 0 1 0 0 JISHUDATA7
28 - - E -- OUTPUT 0 1 0 0 PAUSE
29 - - E -- OUTPUT 0 1 0 0 REV
30 - - F -- OUTPUT 0 1 0 0 RUN
51 - - - 14 OUTPUT 0 1 0 0 SEGOUT0
49 - - - 14 OUTPUT 0 1 0 0 SEGOUT1
48 - - - 15 OUTPUT 0 1 0 0 SEGOUT2
47 - - - 16 OUTPUT 0 1 0 0 SEGOUT3
46 - - - 17 OUTPUT 0 1 0 0 SEGOUT4
44 - - - 18 OUTPUT 0 1 0 0 SEGOUT5
43 - - - 18 OUTPUT 0 1 0 0 SEGOUT6
8 - - A -- OUTPUT 0 1 0 0 SELOUT0
102 - - A -- OUTPUT 0 1 0 0 SELOUT1
97 - - B -- OUTPUT 0 1 0 0 SELOUT2
96 - - B -- OUTPUT 0 1 0 0 SELOUT3
9 - - B -- OUTPUT 0 1 0 0 TJ
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\ss\ss\zuizhongxyjgdf.rpt
zuizhongxyjgdf
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 14 OR2 0 2 0 3 |ZONGXIANSHI:1|couter:u1|LPM_ADD_SUB:225|addcore:adder|pcarry1
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