zuizhongxyjgdf.rpt

自己 写的课程设计

Project Information                                f:\ss\ss\zuizhongxyjgdf.rpt

MAX+plus II Compiler Report File
Version 10.12 09/21/2001
Compiled: 05/15/2007 17:58:06

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

zuizhongxyjgdf
      EPF10K20TC144-3      5      31     0    0         0  %    628      54 %

User Pins:                 5      31     0  



Project Information                                f:\ss\ss\zuizhongxyjgdf.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Line 24: File f:\ss\ss\couter.vhd: Found multiple assignments to the same signal or signal bit "linshi27" in a Process Statement -- only the last assignment will take effect
Warning: Line 24: File f:\ss\ss\couter.vhd: Found multiple assignments to the same signal or signal bit "linshi26" in a Process Statement -- only the last assignment will take effect
Warning: Line 24: File f:\ss\ss\couter.vhd: Found multiple assignments to the same signal or signal bit "linshi25" in a Process Statement -- only the last assignment will take effect
Warning: Line 24: File f:\ss\ss\couter.vhd: Found multiple assignments to the same signal or signal bit "linshi24" in a Process Statement -- only the last assignment will take effect
Warning: Line 24: File f:\ss\ss\couter.vhd: Found multiple assignments to the same signal or signal bit "linshi23" in a Process Statement -- only the last assignment will take effect
Warning: Line 24: File f:\ss\ss\couter.vhd: Found multiple assignments to the same signal or signal bit "linshi22" in a Process Statement -- only the last assignment will take effect
Warning: Line 24: File f:\ss\ss\couter.vhd: Found multiple assignments to the same signal or signal bit "linshi21" in a Process Statement -- only the last assignment will take effect
Warning: Line 24: File f:\ss\ss\couter.vhd: Found multiple assignments to the same signal or signal bit "linshi20" in a Process Statement -- only the last assignment will take effect


Project Information                                f:\ss\ss\zuizhongxyjgdf.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

zuizhongxyjgdf@128                 clk
zuizhongxyjgdf@122                 CP
zuizhongxyjgdf@72                 Ld
zuizhongxyjgdf@28                 PAUSE
zuizhongxyjgdf@29                 REV
zuizhongxyjgdf@30                 RUN
zuizhongxyjgdf@125                 SACNCLK
zuizhongxyjgdf@51                 SEGOUT0
zuizhongxyjgdf@49                 SEGOUT1
zuizhongxyjgdf@48                 SEGOUT2
zuizhongxyjgdf@47                 SEGOUT3
zuizhongxyjgdf@46                 SEGOUT4
zuizhongxyjgdf@44                 SEGOUT5
zuizhongxyjgdf@43                 SEGOUT6
zuizhongxyjgdf@8                  SELOUT0
zuizhongxyjgdf@102                 SELOUT1
zuizhongxyjgdf@97                 SELOUT2
zuizhongxyjgdf@96                 SELOUT3
zuizhongxyjgdf@73                 START
zuizhongxyjgdf@9                  TJ


Project Information                                f:\ss\ss\zuizhongxyjgdf.rpt

** FILE HIERARCHY **



|zongxianshi:1|
|zongxianshi:1|jishu:u0|
|zongxianshi:1|jishu:u0|lpm_add_sub:113|
|zongxianshi:1|jishu:u0|lpm_add_sub:113|addcore:adder|
|zongxianshi:1|jishu:u0|lpm_add_sub:113|altshift:result_ext_latency_ffs|
|zongxianshi:1|jishu:u0|lpm_add_sub:113|altshift:carry_ext_latency_ffs|
|zongxianshi:1|jishu:u0|lpm_add_sub:113|altshift:oflow_ext_latency_ffs|
|zongxianshi:1|couter:u1|
|zongxianshi:1|couter:u1|lpm_add_sub:225|
|zongxianshi:1|couter:u1|lpm_add_sub:225|addcore:adder|
|zongxianshi:1|couter:u1|lpm_add_sub:225|altshift:result_ext_latency_ffs|
|zongxianshi:1|couter:u1|lpm_add_sub:225|altshift:carry_ext_latency_ffs|
|zongxianshi:1|couter:u1|lpm_add_sub:225|altshift:oflow_ext_latency_ffs|
|zongxianshi:1|couter:u1|lpm_add_sub:368|
|zongxianshi:1|couter:u1|lpm_add_sub:368|addcore:adder|
|zongxianshi:1|couter:u1|lpm_add_sub:368|altshift:result_ext_latency_ffs|
|zongxianshi:1|couter:u1|lpm_add_sub:368|altshift:carry_ext_latency_ffs|
|zongxianshi:1|couter:u1|lpm_add_sub:368|altshift:oflow_ext_latency_ffs|
|zongxianshi:1|shixu:u2|
|zongxianshi:1|shixu:u2|lpm_add_sub:98|
|zongxianshi:1|shixu:u2|lpm_add_sub:98|addcore:adder|
|zongxianshi:1|shixu:u2|lpm_add_sub:98|altshift:result_ext_latency_ffs|
|zongxianshi:1|shixu:u2|lpm_add_sub:98|altshift:carry_ext_latency_ffs|
|zongxianshi:1|shixu:u2|lpm_add_sub:98|altshift:oflow_ext_latency_ffs|
|zongxianshi:1|shixu:u2|lpm_add_sub:162|
|zongxianshi:1|shixu:u2|lpm_add_sub:162|addcore:adder|
|zongxianshi:1|shixu:u2|lpm_add_sub:162|altshift:result_ext_latency_ffs|
|zongxianshi:1|shixu:u2|lpm_add_sub:162|altshift:carry_ext_latency_ffs|
|zongxianshi:1|shixu:u2|lpm_add_sub:162|altshift:oflow_ext_latency_ffs|
|zongxianshi:1|yima:u3|
|zongxianshi:1|sevenduan:u4|
|zongxianshi:1|sevenduan:u4|lpm_add_sub:101|
|zongxianshi:1|sevenduan:u4|lpm_add_sub:101|addcore:adder|
|zongxianshi:1|sevenduan:u4|lpm_add_sub:101|altshift:result_ext_latency_ffs|
|zongxianshi:1|sevenduan:u4|lpm_add_sub:101|altshift:carry_ext_latency_ffs|
|zongxianshi:1|sevenduan:u4|lpm_add_sub:101|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                       f:\ss\ss\zuizhongxyjgdf.rpt
zuizhongxyjgdf

***** Logic for device 'zuizhongxyjgdf' compiled without errors.




Device: EPF10K20TC144-3

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f
    MultiVolt I/O                              = OFF

                J       J   J                                                            
                I       I   I                                                            
                S G R R S   S R R R   R R R R                 R R R R R R   R R R R R G  
                H E E E H   H E E E   E E E E         S       E E E E E E   E E E E E E