cepin.vhd

本VHDL源代码由顶层模块、测频模块、驱动模块、计算模块、LCD显示模块、复位模块组成

--/*CEPIN．VHD*/--测频模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cepin is
    Port (bz:in std_logic;
	 		 dc:in std_logic;
			 rst,cl:in std_logic;
			 bzclk,dcclk:out std_logic_vector(31 downto 0));
end cepin;

architecture Behavioral of cepin is
signal ena:std_logic;
signal bzclk1,dcclk1,bzq,dcq:std_logic_vector(31 downto 0);
begin

process(rst,bzclk1,dcclk1)
begin
	if rst'event and rst='1' then
		bzclk<=bzclk1;
		dcclk<=dcclk1;
	end if;
end process;

process(ena,bz,bzq,dcq)
begin
	if bz'event and bz='1' then
		if ena='0' then
			bzclk1<=bzq;
			dcclk1<=dcq;
		end if;
	end if;
end process;

bz1:process(bz,rst,ena)
begin
	if rst='1' then  
		bzq<=(others=>'0');
	elsif rising_edge(bz) then 
		if ena='1' then 
			if bzq(3 downto 0)<9 then 
				bzq(3 downto 0)<=bzq(3 downto 0)+1;
			else
				bzq(3 downto 0)<="0000";
				if bzq(7 downto 4)<9 then 
					bzq(7 downto 4)<=bzq(7 downto 4)+1;
				else
					bzq(7 downto 4)<="0000";
					if bzq(11 downto 8)<9 then 
						bzq(11 downto 8)<=bzq(11 downto 8)+1;
					else
						bzq(11 downto 8)<="0000";
						if bzq(15 downto 12)<9 then
							bzq(15 downto 12)<=bzq(15 downto 12)+1;
						else
							bzq(15 downto 12)<="0000";
							if bzq(19 downto 16)<9 then
								bzq(19 downto 16)<=bzq(19 downto 16)+1;
							else
								bzq(19 downto 16)<="0000";
								if bzq(23 downto 20)<9 then
									bzq(23 downto 20)<=bzq(23 downto 20)+1;
								else
									bzq(23 downto 20)<="0000";
									if bzq(27 downto 24)<9 then
										bzq(27 downto 24)<=bzq(27 downto 24)+1;
									else
										bzq(27 downto 24)<="0000";
										if bzq(31 downto 28)<9 then
										bzq(31 downto 28)<=bzq(31 downto 28)+1;
										else
											bzq(31 downto 28)<="0000";
										end if;
									end if;
								end if;
							end if;
						end if;
					end if;
				end if;
			end if;
		end if;
	end if;
end process bz1;

dc1:process(dc,rst,ena)
begin
	if rst='1' then 
		dcq<=(others=>'0');
	elsif rising_edge(dc) then
		if ena='1' then
			if dcq(3 downto 0)<9 then 
				dcq(3 downto 0)<=dcq(3 downto 0)+1;
			else
				dcq(3 downto 0)<="0000";
				if dcq(7 downto 4)<9 then 
					dcq(7 downto 4)<=dcq(7 downto 4)+1;
				else
					dcq(7 downto 4)<="0000";
					if dcq(11 downto 8)<9 then 
						dcq(11 downto 8)<=dcq(11 downto 8)+1;
					else
						dcq(11 downto 8)<="0000";
						if dcq(15 downto 12)<9 then
							dcq(15 downto 12)<=dcq(15 downto 12)+1;
						else
							dcq(15 downto 12)<="0000";
							if dcq(19 downto 16)<9 then
								dcq(19 downto 16)<=dcq(19 downto 16)+1;
							else
								dcq(19 downto 16)<="0000";
								if dcq(23 downto 20)<9 then
									dcq(23 downto 20)<=dcq(23 downto 20)+1;
								else
									dcq(23 downto 20)<="0000";
									if dcq(27 downto 24)<9 then
										dcq(27 downto 24)<=dcq(27 downto 24)+1;
									else
										dcq(27 downto 24)<="0000";
										if dcq(31 downto 28)<9 then
										dcq(31 downto 28)<=dcq(31 downto 28)+1;
										else
											dcq(31 downto 28)<="0000";
										end if;
									end if;
								end if;
							end if;
						end if;
					end if;
				end if;
			end if; 
		end if;
	end if;
end process dc1;

process(dc,rst,cl)
begin
	if rst='1' then
		ena<='0';
	elsif rising_edge(dc) then 
		ena<=cl;
	end if;
end process;

end Behavioral;