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📄 reset.rpt

📁 本VHDL源代码由顶层模块、测频模块、驱动模块、计算模块、LCD显示模块、复位模块组成
💻 RPT
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   -     22    B       SOFT      t        0      0   0    0   13    2    8  |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|result_node4
 (18)    21    B       SOFT      t        0      0   0    0   14    2    8  |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|result_node5
   -     28    B       SOFT      t        0      0   0    0   15    2    8  |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|result_node6
 (29)    41    C       SOFT      t        0      0   0    0   16    2    8  |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|result_node7
   -     45    C       SOFT      t        0      0   0    0   17    2    8  |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node0
   -     34    C       SOFT      t        0      0   0    0   18    2    8  |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node1
 (25)    35    C       SOFT      t        0      0   0    0   12    2    8  |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node2
 (26)    36    C       SOFT      t        0      0   0    0   13    2    8  |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node3
 (31)    46    C       SOFT      t        0      0   0    0   14    2    8  |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node4
   -     38    C       SOFT      t        0      0   0    0   15    2    8  |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node5
 (32)    48    C       SOFT      t        0      0   0    0   16    2    8  |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node6
   -     47    C       SOFT      t        0      0   0    0   17    2    8  |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node7
   -     44    C       SOFT      t        0      0   0    0   10    2    8  |LPM_ADD_SUB:127|addcore:adder|addcore:adder3|result_node0
 (41)    64    D       DFFE   +  t        0      0   0    1   25    0    1  cnt24 (:9)
 (27)    37    C       TFFE   +  t        0      0   0    1   16    0    2  cnt23 (:10)
 (24)    33    C       TFFE   +  t        0      0   0    1   15    0    4  cnt22 (:11)
   -     63    D       DFFE   +  t        0      0   0    1   25    0    6  cnt21 (:12)
 (40)    62    D       DFFE   +  t        0      0   0    1   25    0    7  cnt20 (:13)
   -     43    C       TFFE   +  t        0      0   0    1   12    0    8  cnt19 (:14)
   -     42    C       TFFE   +  t        0      0   0    1   11    0   10  cnt18 (:15)
 (28)    40    C       TFFE   +  t        0      0   0    1   17    0   12  cnt17 (:16)
   -     61    D       DFFE   +  t        0      0   0    1   25    0   14  cnt16 (:17)
   -     29    B       TFFE   +  t        0      0   0    1   15    0   15  cnt15 (:18)
   -     27    B       TFFE   +  t        0      0   0    1   14    0   17  cnt14 (:19)
   -     58    D       DFFE   +  t        0      0   0    1   25    0   19  cnt13 (:20)
 (19)    20    B       TFFE   +  t        0      0   0    1   12    0   20  cnt12 (:21)
   -     59    D       DFFE   +  t        0      0   0    1   25    0   22  cnt11 (:22)
 (39)    57    D       DFFE   +  t        0      0   0    1   25    0   23  cnt10 (:23)
 (17)    24    B       TFFE   +  t        0      0   0    1    9    0   24  cnt9 (:24)
   -     60    D       DFFE   +  t        0      0   0    1   25    0   26  cnt8 (:25)
 (16)    25    B       TFFE   +  t        0      0   0    1    7    0   18  cnt7 (:26)
   -     26    B       TFFE   +  t        0      0   0    1    6    0   20  cnt6 (:27)
 (38)    56    D       TFFE   +  t        0      0   0    1    5    0   22  cnt5 (:28)
 (36)    52    D       TFFE   +  t        0      0   0    1    4    0   24  cnt4 (:29)
 (37)    53    D       TFFE   +  t        0      0   0    1    3    0   26  cnt3 (:30)
   -     54    D       TFFE   +  t        0      0   0    1    2    0   28  cnt2 (:31)
   -     55    D       TFFE   +  t        0      0   0    1    1    0   30  cnt1 (:32)
   -     50    D       TFFE   +  t        0      0   0    1    0    2   39  cnt0 (:33)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                              c:\pinlvji\reset.rpt
reset

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                   Logic cells placed in LAB 'A'
        +--------- LC13 |LPM_ADD_SUB:127|addcore:adder|addcore:adder0|result_node1
        | +------- LC12 |LPM_ADD_SUB:127|addcore:adder|addcore:adder0|result_node2
        | | +----- LC11 |LPM_ADD_SUB:127|addcore:adder|addcore:adder0|result_node3
        | | | +--- LC14 |LPM_ADD_SUB:127|addcore:adder|addcore:adder0|result_node4
        | | | | +- LC2 |LPM_ADD_SUB:127|addcore:adder|addcore:adder0|result_node5
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'A'
LC      | | | | | | A B C D |     Logic cells that feed LAB 'A':

Pin
43   -> - - - - - | - - - - | <-- clk
LC56 -> - - - - * | * * * - | <-- cnt5
LC52 -> - - - * * | * * * * | <-- cnt4
LC53 -> - - * * * | * * * * | <-- cnt3
LC54 -> - * * * * | * * * * | <-- cnt2
LC55 -> * * * * * | * * * * | <-- cnt1
LC50 -> * * * * * | * * * * | <-- cnt0


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              c:\pinlvji\reset.rpt
reset

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                         Logic cells placed in LAB 'B'
        +------------------------------- LC31 |LPM_ADD_SUB:127|addcore:adder|addcore:adder0|cout_node
        | +----------------------------- LC23 |LPM_ADD_SUB:127|addcore:adder|addcore:adder0|result_node6
        | | +--------------------------- LC19 |LPM_ADD_SUB:127|addcore:adder|addcore:adder0|result_node7
        | | | +------------------------- LC18 |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|result_node0
        | | | | +----------------------- LC17 |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|result_node1
        | | | | | +--------------------- LC32 |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|result_node2
        | | | | | | +------------------- LC30 |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|result_node3
        | | | | | | | +----------------- LC22 |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|result_node4
        | | | | | | | | +--------------- LC21 |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|result_node5
        | | | | | | | | | +------------- LC28 |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|result_node6
        | | | | | | | | | | +----------- LC29 cnt15
        | | | | | | | | | | | +--------- LC27 cnt14
        | | | | | | | | | | | | +------- LC20 cnt12
        | | | | | | | | | | | | | +----- LC24 cnt9
        | | | | | | | | | | | | | | +--- LC25 cnt7
        | | | | | | | | | | | | | | | +- LC26 cnt6
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'B':
LC27 -> - - - - - - - - - * * * - - - - | - * * - | <-- cnt14
LC20 -> - - - - - - - * * * * * * - - - | - * * - | <-- cnt12
LC24 -> - - - - * * * * * * * * * * - - | - * * - | <-- cnt9
LC25 -> * - * * * * * * * * * * * * * - | - * * - | <-- cnt7
LC26 -> * * * * * * * * * * * * * * * * | - * * - | <-- cnt6

Pin
43   -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
12   -> - - - - - - - - - - * * * * * * | - * * * | <-- rst
LC58 -> - - - - - - - - * * * * - - - - | - * * - | <-- cnt13
LC59 -> - - - - - - * * * * * * * - - - | - * * - | <-- cnt11
LC57 -> - - - - - * * * * * * * * - - - | - * * - | <-- cnt10
LC60 -> - - - * * * * * * * * * * * - - | - * * - | <-- cnt8
LC56 -> * * * * * * * * * * * * * * * * | * * * - | <-- cnt5
LC52 -> * * * * * * * * * * * * * * * * | * * * * | <-- cnt4
LC53 -> * * * * * * * * * * * * * * * * | * * * * | <-- cnt3
LC54 -> * * * * * * * * * * * * * * * * | * * * * | <-- cnt2
LC55 -> * * * * * * * * * * * * * * * * | * * * * | <-- cnt1
LC50 -> * * * * * * * * * * * * * * * * | * * * * | <-- cnt0


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              c:\pinlvji\reset.rpt
reset

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                         Logic cells placed in LAB 'C'
        +------------------------------- LC39 |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|cout_node
        | +----------------------------- LC41 |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|result_node7
        | | +--------------------------- LC45 |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node0
        | | | +------------------------- LC34 |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node1
        | | | | +----------------------- LC35 |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node2
        | | | | | +--------------------- LC36 |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node3
        | | | | | | +------------------- LC46 |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node4
        | | | | | | | +----------------- LC38 |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node5
        | | | | | | | | +--------------- LC48 |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node6
        | | | | | | | | | +------------- LC47 |LPM_ADD_SUB:127|addcore:adder|addcore:adder2|result_node7
        | | | | | | | | | | +----------- LC44 |LPM_ADD_SUB:127|addcore:adder|addcore:adder3|result_node0
        | | | | | | | | | | | +--------- LC37 cnt23
        | | | | | | | | | | | | +------- LC33 cnt22
        | | | | | | | | | | | | | +----- LC43 cnt19
        | | | | | | | | | | | | | | +--- LC42 cnt18
        | | | | | | | | | | | | | | | +- LC40 cnt17
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'C':
LC39 -> - - - - - - - - - - * - - - - - | - - * - | <-- |LPM_ADD_SUB:127|addcore:adder|addcore:adder1|cout_node
LC37 -> - - - - - - - - - * * * - - - - | - - * - | <-- cnt23
LC33 -> - - - - - - - - * * * * * - - - | - - * - | <-- cnt22
LC43 -> - - - - - * * * * * * * * * - - | - - * - | <-- cnt19
LC42 -> - - - - * * * * * * * * * * * - | - - * - | <-- cnt18
LC40 -> - - - * * * * * * * * * * * * * | - - * - | <-- cnt17

Pin
43   -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
12   -> - - - - - - - - - - - * * * * * | - * * * | <-- rst
LC31 -> - - - - * * * * * * - * * * * - | - - * - | <-- |LPM_ADD_SUB:127|addcore:adder|addcore:adder0|cout_node
LC64 -> - - - - - - - - - - * - - - - - | - - * - | <-- cnt24
LC63 -> - - - - - - - * * * * * * - - - | - - * - | <-- cnt21
LC62 -> - - - - - - * * * * * * * - - - | - - * - | <-- cnt20
LC61 -> - - * * * * * * * * * * * * * * | - - * - | <-- cnt16
LC29 -> * * * * * * * * * * - * * * * * | - - * - | <-- cnt15
LC27 -> * * * * * * * * * * - * * * * * | - * * - | <-- cnt14
LC58 -> * * * * * * * * * * - * * * * * | - * * - | <-- cnt13
LC20 -> * * * * * * * * * * - * * * * * | - * * - | <-- cnt12
LC59 -> * * * * * * * * * * - * * * * * | - * * - | <-- cnt11
LC57 -> * * * * * * * * * * - * * * * * | - * * - | <-- cnt10
LC24 -> * * * * * * * * * * - * * * * * | - * * - | <-- cnt9
LC60 -> * * * * * * * * * * - * * * * * | - * * - | <-- cnt8
LC25 -> * * * * - - - - - - - - - - - * | - * * - | <-- cnt7
LC26 -> * * * * - - - - - - - - - - - * | - * * - | <-- cnt6
LC56 -> * * * * - - - - - - - - - - - * | * * * - | <-- cnt5
LC52 -> * * * * - - - - - - - - - - - * | * * * * | <-- cnt4
LC53 -> * * * * - - - - - - - - - - - * | * * * * | <-- cnt3
LC54 -> * * * * - - - - - - - - - - - * | * * * * | <-- cnt2
LC55 -> * * * * - - - - - - - - - - - * | * * * * | <-- cnt1
LC50 -> * * * * - - - - - - - - - - - * | * * * * | <-- cnt0


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              c:\pinlvji\reset.rpt
reset

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                         Logic cells placed in LAB 'D'
        +------------------------------- LC49 cl
        | +----------------------------- LC51 clr
        | | +--------------------------- LC64 cnt24
        | | | +------------------------- LC63 cnt21
        | | | | +----------------------- LC62 cnt20
        | | | | | +--------------------- LC61 cnt16
        | | | | | | +------------------- LC58 cnt13
        | | | | | | | +----------------- LC59 cnt11
        | | | | | | | | +--------------- LC57 cnt10
        | | | | | | | | | +------------- LC60 cnt8
        | | | | | | | | | | +----------- LC56 cnt5
        | | | | | | | | | | | +--------- LC52 cnt4
        | | | | | | | | | | | | +------- LC53 cnt3
        | | | | | | | | | | | | | +----- LC54 cnt2
        | | | | | | | | | | | | | | +--- LC55 cnt1
        | | | | | | | | | | | | | | | +- LC50 cnt0
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC49 -> * - - - - - - - - - - - - - - - | - - - * | <-- cl
LC51 -> - * - - - - - - - - - - - - - - | - - - * | <-- clr

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