jisuan.hif

本VHDL源代码由顶层模块、测频模块、驱动模块、计算模块、LCD显示模块、复位模块组成

HIF003
--
-- Copyright (C) 1988-2003 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	div.vhd
	{
		div [] [U5125632.DLS,U9092257.DLS,U9234712.DLS,U9587408.DLS,U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			1 [] [];
		}
	}
	jisuan.vhd
	{
		jisuan [] [U1147235.DLS,U7449008.DLS,U2043679.DLS,U9587408.DLS,U9234712.DLS,U9092257.DLS,U5125632.DLS]
		{
			0 [] [];
		}
	}
}
TREE
{
	jisuan::(0,0):(0): jisuan.vhd
	{
		div:1:(33,4):(264,u1): div.vhd;
	}
}