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📄 cepin.rpt

📁 本VHDL源代码由顶层模块、测频模块、驱动模块、计算模块、LCD显示模块、复位模块组成
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   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~8081~3
   -     ??   ??       SOFT    s t        1      0   1    0   17    0    1  ~8081~4
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~8081~5
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~8081~6
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~8081~7
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~8081~8
   -     ??   ??       SOFT    s t        1      0   1    0   14    0    1  ~8081~9
   -     ??   ??       SOFT    s t        1      0   1    0   16    0    1  ~8081~10
   -     ??   ??       SOFT    s t        1      0   1    0   14    0    1  ~8081~11
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~8317~1
   -     ??   ??       SOFT    s t        1      0   1    0   17    0    1  ~8317~2
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~8317~3
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~8317~4
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~8317~5
   -     ??   ??       SOFT    s t        1      0   1    0   14    0    1  ~8323~1
   -     ??   ??       SOFT    s t        0      0   0    0    4    0   49  ~9303~1
   -     ??   ??       SOFT    s t        6      2   1    0   17    0    1  ~13969~1
   -     ??   ??       SOFT    s t        0      0   0    0    4    0   37  ~13974~1
   -     ??   ??       SOFT    s t       15      0   1    0   25    0    1  ~13978~1
   -     ??   ??       SOFT    s t        1      0   1    0   12    0    1  ~13978~2
   -     ??   ??       SOFT    s t        1      0   1    0   12    0    1  ~13978~3
   -     ??   ??       SOFT    s t        1      0   1    0   14    0    1  ~13978~4
   -     ??   ??       SOFT    s t        1      0   1    0   12    0    1  ~13978~5
   -     ??   ??       SOFT    s t        1      0   1    0   12    0    1  ~13978~6
   -     ??   ??       SOFT    s t        1      0   1    0   11    0    1  ~13978~7
   -     ??   ??       SOFT    s t        1      0   1    0   11    0    1  ~13978~8
   -     ??   ??       SOFT    s t        1      0   1    0   10    0    1  ~13978~9
   -     ??   ??       SOFT    s t        1      0   1    0   12    0    1  ~13978~10
   -     ??   ??       SOFT    s t        0      0   0    0    4    0   42  ~14142~1
   -     ??   ??       SOFT    s t        0      0   0    0    4    0    1  ~14147~1
   -     ??   ??       SOFT    s t        0      0   0    0    4    0    1  ~14153~1
   -     ??   ??       SOFT    s t        0      0   0    0    3    0    1  ~14329~1
   -     ??   ??       SOFT    s t        0      0   0    0    4    0   36  ~14333~1
   -     ??   ??       SOFT    s t        0      0   0    0    3    0    1  ~14338~1
   -     ??   ??       SOFT    s t        0      0   0    0    3    0    1  ~14540~1
   -     ??   ??       SOFT    s t        0      0   0    0    3    0    1  ~14549~1
   -     ??   ??       SOFT    s t       13      0   1    0   29    0    1  ~14557~1
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~14557~2
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~14557~3
   -     ??   ??       SOFT    s t        1      0   1    0   17    0    1  ~14557~4
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~14557~5
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~14557~6
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~14557~7
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~14557~8
   -     ??   ??       SOFT    s t        1      0   1    0   14    0    1  ~14557~9
   -     ??   ??       SOFT    s t        1      0   1    0   16    0    1  ~14557~10
   -     ??   ??       SOFT    s t        1      0   1    0   14    0    1  ~14557~11
   -     ??   ??       SOFT    s t        1      0   1    0   16    0    1  ~14793~1
   -     ??   ??       SOFT    s t        1      0   1    0   16    0    1  ~14793~2
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~14793~3
   -     ??   ??       SOFT    s t        1      0   1    0   17    0    1  ~14793~4
   -     ??   ??       SOFT    s t        1      0   1    0   15    0    1  ~14793~5
   -     ??   ??       SOFT    s t        1      0   1    0   14    0    1  ~14799~1
   -     ??   ??       SOFT    s t        1      0   1    0   16    0    1  ~14805~1


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                              c:\pinlvji\cepin.rpt
cepin

** EQUATIONS **

bz       : INPUT;
cl       : INPUT;
dc       : INPUT;
rst      : INPUT;

-- Node name is 'bzclk0' = ':67' 
-- Equation name is 'bzclk0', type is output 
 bzclk0  = DFFE( bzclk10~39 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk1' = ':65' 
-- Equation name is 'bzclk1', type is output 
 bzclk1  = DFFE( bzclk11~39 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk2' = ':63' 
-- Equation name is 'bzclk2', type is output 
 bzclk2  = DFFE( bzclk12~39 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk3' = ':61' 
-- Equation name is 'bzclk3', type is output 
 bzclk3  = DFFE( bzclk13~39 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk4' = ':59' 
-- Equation name is 'bzclk4', type is output 
 bzclk4  = DFFE( bzclk14~39 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk5' = ':57' 
-- Equation name is 'bzclk5', type is output 
 bzclk5  = DFFE( bzclk15~39 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk6' = ':55' 
-- Equation name is 'bzclk6', type is output 
 bzclk6  = DFFE( bzclk16~39 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk7' = ':53' 
-- Equation name is 'bzclk7', type is output 
 bzclk7  = DFFE( bzclk17~39 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk8' = ':51' 
-- Equation name is 'bzclk8', type is output 
 bzclk8  = DFFE( bzclk18~39 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk9' = ':49' 
-- Equation name is 'bzclk9', type is output 
 bzclk9  = DFFE( bzclk19~39 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is ':164' = 'bzclk10~39' 
-- Equation name is 'bzclk10~39', type is buried 
bzclk10~39 = DFFE( _EQ001 $  GND, GLOBAL( bz),  VCC,  VCC,  VCC);
  _EQ001 =  bzclk10~39 &  ena
         #  bzq0 & !ena;

-- Node name is 'bzclk10' = ':47' 
-- Equation name is 'bzclk10', type is output 
 bzclk10 = DFFE( bzclk110 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is ':163' = 'bzclk11~39' 
-- Equation name is 'bzclk11~39', type is buried 
bzclk11~39 = DFFE( _EQ002 $  GND, GLOBAL( bz),  VCC,  VCC,  VCC);
  _EQ002 =  bzclk11~39 &  ena
         #  bzq1 & !ena;

-- Node name is 'bzclk11' = ':45' 
-- Equation name is 'bzclk11', type is output 
 bzclk11 = DFFE( bzclk111 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is ':162' = 'bzclk12~39' 
-- Equation name is 'bzclk12~39', type is buried 
bzclk12~39 = DFFE( _EQ003 $  GND, GLOBAL( bz),  VCC,  VCC,  VCC);
  _EQ003 =  bzclk12~39 &  ena
         #  bzq2 & !ena;

-- Node name is 'bzclk12' = ':43' 
-- Equation name is 'bzclk12', type is output 
 bzclk12 = DFFE( bzclk112 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is ':161' = 'bzclk13~39' 
-- Equation name is 'bzclk13~39', type is buried 
bzclk13~39 = DFFE( _EQ004 $  GND, GLOBAL( bz),  VCC,  VCC,  VCC);
  _EQ004 =  bzclk13~39 &  ena
         #  bzq3 & !ena;

-- Node name is 'bzclk13' = ':41' 
-- Equation name is 'bzclk13', type is output 
 bzclk13 = DFFE( bzclk113 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is ':160' = 'bzclk14~39' 
-- Equation name is 'bzclk14~39', type is buried 
bzclk14~39 = DFFE( _EQ005 $  GND, GLOBAL( bz),  VCC,  VCC,  VCC);
  _EQ005 =  bzclk14~39 &  ena
         #  bzq4 & !ena;

-- Node name is 'bzclk14' = ':39' 
-- Equation name is 'bzclk14', type is output 
 bzclk14 = DFFE( bzclk114 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is ':159' = 'bzclk15~39' 
-- Equation name is 'bzclk15~39', type is buried 
bzclk15~39 = DFFE( _EQ006 $  GND, GLOBAL( bz),  VCC,  VCC,  VCC);
  _EQ006 =  bzclk15~39 &  ena
         #  bzq5 & !ena;

-- Node name is 'bzclk15' = ':37' 
-- Equation name is 'bzclk15', type is output 
 bzclk15 = DFFE( bzclk115 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is ':158' = 'bzclk16~39' 
-- Equation name is 'bzclk16~39', type is buried 
bzclk16~39 = DFFE( _EQ007 $  GND, GLOBAL( bz),  VCC,  VCC,  VCC);
  _EQ007 =  bzclk16~39 &  ena
         #  bzq6 & !ena;

-- Node name is 'bzclk16' = ':35' 
-- Equation name is 'bzclk16', type is output 
 bzclk16 = DFFE( bzclk116 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is ':157' = 'bzclk17~39' 
-- Equation name is 'bzclk17~39', type is buried 
bzclk17~39 = DFFE( _EQ008 $  GND, GLOBAL( bz),  VCC,  VCC,  VCC);
  _EQ008 =  bzclk17~39 &  ena
         #  bzq7 & !ena;

-- Node name is 'bzclk17' = ':33' 
-- Equation name is 'bzclk17', type is output 
 bzclk17 = DFFE( bzclk117 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is ':156' = 'bzclk18~39' 
-- Equation name is 'bzclk18~39', type is buried 
bzclk18~39 = DFFE( _EQ009 $  GND, GLOBAL( bz),  VCC,  VCC,  VCC);
  _EQ009 =  bzclk18~39 &  ena
         #  bzq8 & !ena;

-- Node name is 'bzclk18' = ':31' 
-- Equation name is 'bzclk18', type is output 
 bzclk18 = DFFE( bzclk118 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is ':155' = 'bzclk19~39' 
-- Equation name is 'bzclk19~39', type is buried 
bzclk19~39 = DFFE( _EQ010 $  GND, GLOBAL( bz),  VCC,  VCC,  VCC);
  _EQ010 =  bzclk19~39 &  ena
         #  bzq9 & !ena;

-- Node name is 'bzclk19' = ':29' 
-- Equation name is 'bzclk19', type is output 
 bzclk19 = DFFE( bzclk119 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk20' = ':27' 
-- Equation name is 'bzclk20', type is output 
 bzclk20 = DFFE( bzclk120 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk21' = ':25' 
-- Equation name is 'bzclk21', type is output 
 bzclk21 = DFFE( bzclk121 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk22' = ':23' 
-- Equation name is 'bzclk22', type is output 
 bzclk22 = DFFE( bzclk122 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk23' = ':21' 
-- Equation name is 'bzclk23', type is output 
 bzclk23 = DFFE( bzclk123 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk24' = ':19' 
-- Equation name is 'bzclk24', type is output 
 bzclk24 = DFFE( bzclk124 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk25' = ':17' 
-- Equation name is 'bzclk25', type is output 
 bzclk25 = DFFE( bzclk125 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk26' = ':15' 
-- Equation name is 'bzclk26', type is output 
 bzclk26 = DFFE( bzclk126 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk27' = ':13' 
-- Equation name is 'bzclk27', type is output 
 bzclk27 = DFFE( bzclk127 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk28' = ':11' 
-- Equation name is 'bzclk28', type is output 
 bzclk28 = DFFE( bzclk128 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk29' = ':9' 
-- Equation name is 'bzclk29', type is output 
 bzclk29 = DFFE( bzclk129 $  GND,  rst,  VCC,  VCC,  VCC);

-- Node name is 'bzclk30' = ':7' 
-- Equation name is 'bzclk30', type is output 
 bzclk30 = DFFE( bzclk130 $  GND,  rst,  VCC,  VCC,  VCC);

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