📄 div.vhd
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--/*DIV.VHD*/--串行BCD码除法模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity div is
Port (clk,rst:in std_logic;
bei,chu:in std_logic_vector(31 downto 0);
shang:out std_logic_vector(31 downto 0);
dian:out integer range -10 to 10 );
end div;
architecture Behavioral of div is
type ss is array (1 to 8) of std_logic_vector(3 downto 0);
signal s:ss;
signal a,b:std_logic_vector(31 downto 0);
signal n:integer range -10 to 10;
signal c:integer range 0 to 8;
signal k:integer range 1 to 7;
signal d:integer range 0 to 1;
begin
process(clk,k,n,c,s,bei,chu,a,b,rst)
variable cnt:integer range 0 to 31;
variable m:std_logic_vector(3 downto 0);
begin
if rst='0' then
k<=5;n<=7;c<=8;cnt:=0;m:="0000";s<=(("0000"),("0000"),("0000"),("0000"),("0000"),("0000"),("0000"),("0000"));
shang<=(others=>'0');
elsif rising_edge(clk) then
case k is
when 1=>if b(31 downto 28)=0 then
b<=b(27 downto 0)&"0000";
if n<10 then
n<=n+1;
else
k<=5;
n<=7;
end if;
else
k<=2;
end if;
when 2=>if a<b then
b<="0000"&b(31 downto 4);
n<=n-1;
else
if n=0 then
k<=5;
n<=7;
else
k<=3;
end if;
end if;
when 3=> if a(cnt+3 downto cnt)>=b(cnt+3 downto cnt)+d then
a(cnt+3 downto cnt)<=a(cnt+3 downto cnt)-b(cnt+3 downto cnt)-d;
d<=0;
else
a(cnt+3 downto cnt)<=a(cnt+3 downto cnt)+10-b(cnt+03 downto cnt)-d;
d<=1;
end if;
if cnt<28 then
cnt:=cnt+4;
k<=3;
else
k<=4;
end if;
when 4=> m:=m+1;
cnt:=0;
d<=0;
if a<=b then
s(c)<=m;
m:="0000";
if c=1 then
k<=5;
else
k<=7;
c<=c-1;
if a(31 downto 28)=0 then
a<=a(27 downto 0)&"0000";
else
b<="0000"&b(31 downto 4);
end if;
end if;
else
k<=3;
end if;
when 7=>if a>=b then
k<=3;
else
a<=a(27 downto 0)&"0000";
s(c)<=m;
if c>=2 then
c<=c-1;
else
k<=5;
end if;
end if;
when 5=>a<=bei;
b<=chu;
shang<=s(8)&s(7)&s(6)&s(5)&s(4)&s(3)&s(2)&s(1);
k<=6;
dian<=n;
n<=7;
m:="0000";
c<=8;
cnt:=0;
when 6=>if a(31 downto 28)=0 then
a<=a(27 downto 0)&"0000";
if n>=0 then
n<=n-1;
else
n<=7;
k<=5;
end if;
else
k<=1;
end if;
when others=>k<=5;
end case;
end if;
end process;
end Behavioral;
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