crc_32.tan.qmsg

crc校验功能

{ "Info" "ITDB_FULL_TCO_RESULT" "clk crc_out\[10\] crc_result_reg\[10\] 8.882 ns register " "Info: tco from clock \"clk\" to destination pin \"crc_out\[10\]\" through register \"crc_result_reg\[10\]\" is 8.882 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.032 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.032 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 48 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 48; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { clk } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.712 ns) + CELL(0.560 ns) 3.032 ns crc_result_reg\[10\] 2 REG LC_X25_Y22_N7 2 " "Info: 2: + IC(1.712 ns) + CELL(0.560 ns) = 3.032 ns; Loc. = LC_X25_Y22_N7; Fanout = 2; REG Node = 'crc_result_reg\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.272 ns" { clk crc_result_reg[10] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 43.54 % ) " "Info: Total cell delay = 1.320 ns ( 43.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.712 ns ( 56.46 % ) " "Info: Total interconnect delay = 1.712 ns ( 56.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[10] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.674 ns + Longest register pin " "Info: + Longest register to pin delay is 5.674 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns crc_result_reg\[10\] 1 REG LC_X25_Y22_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y22_N7; Fanout = 2; REG Node = 'crc_result_reg\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_result_reg[10] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.873 ns) + CELL(2.801 ns) 5.674 ns crc_out\[10\] 2 PIN PIN_AB14 0 " "Info: 2: + IC(2.873 ns) + CELL(2.801 ns) = 5.674 ns; Loc. = PIN_AB14; Fanout = 0; PIN Node = 'crc_out\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "5.674 ns" { crc_result_reg[10] crc_out[10] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.801 ns ( 49.37 % ) " "Info: Total cell delay = 2.801 ns ( 49.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.873 ns ( 50.63 % ) " "Info: Total interconnect delay = 2.873 ns ( 50.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "5.674 ns" { crc_result_reg[10] crc_out[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.674 ns" { crc_result_reg[10] crc_out[10] } { 0.000ns 2.873ns } { 0.000ns 2.801ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[10] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "5.674 ns" { crc_result_reg[10] crc_out[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.674 ns" { crc_result_reg[10] crc_out[10] } { 0.000ns 2.873ns } { 0.000ns 2.801ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "data_in_reg\[7\] data_in\[7\] clk -2.324 ns register " "Info: th for register \"data_in_reg\[7\]\" (data pin = \"data_in\[7\]\", clock pin = \"clk\") is -2.324 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.032 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.032 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 48 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 48; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { clk } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.712 ns) + CELL(0.560 ns) 3.032 ns data_in_reg\[7\] 2 REG LC_X21_Y22_N2 1 " "Info: 2: + IC(1.712 ns) + CELL(0.560 ns) = 3.032 ns; Loc. = LC_X21_Y22_N2; Fanout = 1; REG Node = 'data_in_reg\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.272 ns" { clk data_in_reg[7] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 43.54 % ) " "Info: Total cell delay = 1.320 ns ( 43.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.712 ns ( 56.46 % ) " "Info: Total interconnect delay = 1.712 ns ( 56.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk data_in_reg[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 data_in_reg[7] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 22 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.456 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.456 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 1.020 ns data_in\[7\] 1 PIN PIN_B12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.020 ns) = 1.020 ns; Loc. = PIN_B12; Fanout = 1; PIN Node = 'data_in\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[7] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.346 ns) + CELL(0.090 ns) 5.456 ns data_in_reg\[7\] 2 REG LC_X21_Y22_N2 1 " "Info: 2: + IC(4.346 ns) + CELL(0.090 ns) = 5.456 ns; Loc. = LC_X21_Y22_N2; Fanout = 1; REG Node = 'data_in_reg\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "4.436 ns" { data_in[7] data_in_reg[7] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.110 ns ( 20.34 % ) " "Info: Total cell delay = 1.110 ns ( 20.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.346 ns ( 79.66 % ) " "Info: Total interconnect delay = 4.346 ns ( 79.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "5.456 ns" { data_in[7] data_in_reg[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.456 ns" { data_in[7] data_in[7]~out0 data_in_reg[7] } { 0.000ns 0.000ns 4.346ns } { 0.000ns 1.020ns 0.090ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk data_in_reg[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 data_in_reg[7] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "5.456 ns" { data_in[7] data_in_reg[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.456 ns" { data_in[7] data_in[7]~out0 data_in_reg[7] } { 0.000ns 0.000ns 4.346ns } { 0.000ns 1.020ns 0.090ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITAN_REQUIREMENTS_MET" "" "Info: All timing requirements were met. See Report window for more details." {  } {  } 0 0 "All timing requirements were met. See Report window for more details." 0 0}