crc_32.tan.qmsg

crc校验功能

{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register crc_result_reg\[24\] register crc_result_reg\[8\] 7.378 ns " "Info: Slack time is 7.378 ns for clock \"clk\" between source register \"crc_result_reg\[24\]\" and destination register \"crc_result_reg\[8\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "381.39 MHz 2.622 ns " "Info: Fmax is 381.39 MHz (period= 2.622 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.781 ns + Largest register register " "Info: + Largest register to register requirement is 9.781 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 10.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 10.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.033 ns + Largest " "Info: + Largest clock skew is -0.033 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.999 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 48 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 48; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { clk } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.679 ns) + CELL(0.560 ns) 2.999 ns crc_result_reg\[8\] 2 REG LC_X29_Y22_N7 2 " "Info: 2: + IC(1.679 ns) + CELL(0.560 ns) = 2.999 ns; Loc. = LC_X29_Y22_N7; Fanout = 2; REG Node = 'crc_result_reg\[8\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.239 ns" { clk crc_result_reg[8] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 44.01 % ) " "Info: Total cell delay = 1.320 ns ( 44.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.679 ns ( 55.99 % ) " "Info: Total interconnect delay = 1.679 ns ( 55.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.999 ns" { clk crc_result_reg[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.999 ns" { clk clk~out0 crc_result_reg[8] } { 0.000ns 0.000ns 1.679ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.032 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.032 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 48 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 48; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { clk } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.712 ns) + CELL(0.560 ns) 3.032 ns crc_result_reg\[24\] 2 REG LC_X22_Y22_N1 11 " "Info: 2: + IC(1.712 ns) + CELL(0.560 ns) = 3.032 ns; Loc. = LC_X22_Y22_N1; Fanout = 11; REG Node = 'crc_result_reg\[24\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.272 ns" { clk crc_result_reg[24] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 43.54 % ) " "Info: Total cell delay = 1.320 ns ( 43.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.712 ns ( 56.46 % ) " "Info: Total interconnect delay = 1.712 ns ( 56.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[24] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[24] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.999 ns" { clk crc_result_reg[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.999 ns" { clk clk~out0 crc_result_reg[8] } { 0.000ns 0.000ns 1.679ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[24] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[24] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns - " "Info: - Micro setup delay of destination is 0.010 ns" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.999 ns" { clk crc_result_reg[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.999 ns" { clk clk~out0 crc_result_reg[8] } { 0.000ns 0.000ns 1.679ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[24] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[24] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.403 ns - Longest register register " "Info: - Longest register to register delay is 2.403 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns crc_result_reg\[24\] 1 REG LC_X22_Y22_N1 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y22_N1; Fanout = 11; REG Node = 'crc_result_reg\[24\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_result_reg[24] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.213 ns) 1.580 ns crc_result\[3\]~805 2 COMB LC_X29_Y22_N6 1 " "Info: 2: + IC(1.367 ns) + CELL(0.213 ns) = 1.580 ns; Loc. = LC_X29_Y22_N6; Fanout = 1; COMB Node = 'crc_result\[3\]~805'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "1.580 ns" { crc_result_reg[24] crc_result[3]~805 } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.334 ns) + CELL(0.489 ns) 2.403 ns crc_result_reg\[8\] 3 REG LC_X29_Y22_N7 2 " "Info: 3: + IC(0.334 ns) + CELL(0.489 ns) = 2.403 ns; Loc. = LC_X29_Y22_N7; Fanout = 2; REG Node = 'crc_result_reg\[8\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "0.823 ns" { crc_result[3]~805 crc_result_reg[8] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.702 ns ( 29.21 % ) " "Info: Total cell delay = 0.702 ns ( 29.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.701 ns ( 70.79 % ) " "Info: Total interconnect delay = 1.701 ns ( 70.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.403 ns" { crc_result_reg[24] crc_result[3]~805 crc_result_reg[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.403 ns" { crc_result_reg[24] crc_result[3]~805 crc_result_reg[8] } { 0.000ns 1.367ns 0.334ns } { 0.000ns 0.213ns 0.489ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.999 ns" { clk crc_result_reg[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.999 ns" { clk clk~out0 crc_result_reg[8] } { 0.000ns 0.000ns 1.679ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[24] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[24] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.403 ns" { crc_result_reg[24] crc_result[3]~805 crc_result_reg[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.403 ns" { crc_result_reg[24] crc_result[3]~805 crc_result_reg[8] } { 0.000ns 1.367ns 0.334ns } { 0.000ns 0.213ns 0.489ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register crc_result_reg\[19\] register crc_result_reg\[29\] 918 ps " "Info: Minimum slack time is 918 ps for clock \"clk\" between source register \"crc_result_reg\[19\]\" and destination register \"crc_result_reg\[29\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.842 ns + Shortest register register " "Info: + Shortest register to register delay is 0.842 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns crc_result_reg\[19\] 1 REG LC_X23_Y22_N7 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y22_N7; Fanout = 9; REG Node = 'crc_result_reg\[19\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_result_reg[19] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.607 ns) + CELL(0.235 ns) 0.842 ns crc_result_reg\[29\] 2 REG LC_X24_Y22_N1 6 " "Info: 2: + IC(0.607 ns) + CELL(0.235 ns) = 0.842 ns; Loc. = LC_X24_Y22_N1; Fanout = 6; REG Node = 'crc_result_reg\[29\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "0.842 ns" { crc_result_reg[19] crc_result_reg[29] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.235 ns ( 27.91 % ) " "Info: Total cell delay = 0.235 ns ( 27.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.607 ns ( 72.09 % ) " "Info: Total interconnect delay = 0.607 ns ( 72.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "0.842 ns" { crc_result_reg[19] crc_result_reg[29] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "0.842 ns" { crc_result_reg[19] crc_result_reg[29] } { 0.000ns 0.607ns } { 0.000ns 0.235ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.076 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.076 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 10.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 10.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.032 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.032 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 48 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 48; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { clk } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.712 ns) + CELL(0.560 ns) 3.032 ns crc_result_reg\[29\] 2 REG LC_X24_Y22_N1 6 " "Info: 2: + IC(1.712 ns) + CELL(0.560 ns) = 3.032 ns; Loc. = LC_X24_Y22_N1; Fanout = 6; REG Node = 'crc_result_reg\[29\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.272 ns" { clk crc_result_reg[29] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 43.54 % ) " "Info: Total cell delay = 1.320 ns ( 43.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.712 ns ( 56.46 % ) " "Info: Total interconnect delay = 1.712 ns ( 56.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[29] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[29] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.032 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.032 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 48 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 48; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { clk } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.712 ns) + CELL(0.560 ns) 3.032 ns crc_result_reg\[19\] 2 REG LC_X23_Y22_N7 9 " "Info: 2: + IC(1.712 ns) + CELL(0.560 ns) = 3.032 ns; Loc. = LC_X23_Y22_N7; Fanout = 9; REG Node = 'crc_result_reg\[19\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.272 ns" { clk crc_result_reg[19] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 43.54 % ) " "Info: Total cell delay = 1.320 ns ( 43.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.712 ns ( 56.46 % ) " "Info: Total interconnect delay = 1.712 ns ( 56.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[19] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[19] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[29] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[29] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[19] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[19] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[29] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[29] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[19] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[19] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "0.842 ns" { crc_result_reg[19] crc_result_reg[29] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "0.842 ns" { crc_result_reg[19] crc_result_reg[29] } { 0.000ns 0.607ns } { 0.000ns 0.235ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[29] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[29] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.032 ns" { clk crc_result_reg[19] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.032 ns" { clk clk~out0 crc_result_reg[19] } { 0.000ns 0.000ns 1.712ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "data_in_reg\[10\] data_in\[10\] clk 3.198 ns register " "Info: tsu for register \"data_in_reg\[10\]\" (data pin = \"data_in\[10\]\", clock pin = \"clk\") is 3.198 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.224 ns + Longest pin register " "Info: + Longest pin to register delay is 6.224 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns data_in\[10\] 1 PIN PIN_AB13 1 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_AB13; Fanout = 1; PIN Node = 'data_in\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[10] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.848 ns) + CELL(0.235 ns) 6.224 ns data_in_reg\[10\] 2 REG LC_X25_Y21_N2 1 " "Info: 2: + IC(4.848 ns) + CELL(0.235 ns) = 6.224 ns; Loc. = LC_X25_Y21_N2; Fanout = 1; REG Node = 'data_in_reg\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "5.083 ns" { data_in[10] data_in_reg[10] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.376 ns ( 22.11 % ) " "Info: Total cell delay = 1.376 ns ( 22.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.848 ns ( 77.89 % ) " "Info: Total interconnect delay = 4.848 ns ( 77.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "6.224 ns" { data_in[10] data_in_reg[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.224 ns" { data_in[10] data_in[10]~out0 data_in_reg[10] } { 0.000ns 0.000ns 4.848ns } { 0.000ns 1.141ns 0.235ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.036 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.036 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 48 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 48; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { clk } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.716 ns) + CELL(0.560 ns) 3.036 ns data_in_reg\[10\] 2 REG LC_X25_Y21_N2 1 " "Info: 2: + IC(1.716 ns) + CELL(0.560 ns) = 3.036 ns; Loc. = LC_X25_Y21_N2; Fanout = 1; REG Node = 'data_in_reg\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.276 ns" { clk data_in_reg[10] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 43.48 % ) " "Info: Total cell delay = 1.320 ns ( 43.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.716 ns ( 56.52 % ) " "Info: Total interconnect delay = 1.716 ns ( 56.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.036 ns" { clk data_in_reg[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.036 ns" { clk clk~out0 data_in_reg[10] } { 0.000ns 0.000ns 1.716ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "6.224 ns" { data_in[10] data_in_reg[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.224 ns" { data_in[10] data_in[10]~out0 data_in_reg[10] } { 0.000ns 0.000ns 4.848ns } { 0.000ns 1.141ns 0.235ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "3.036 ns" { clk data_in_reg[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.036 ns" { clk clk~out0 data_in_reg[10] } { 0.000ns 0.000ns 1.716ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}