crc_32.fit.qmsg

crc校验功能

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.317 ns register register " "Info: Estimated most critical path is register to register delay of 2.317 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns crc_result_reg\[17\] 1 REG LAB_X25_Y22 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X25_Y22; Fanout = 8; REG Node = 'crc_result_reg\[17\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_result_reg[17] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.459 ns) 1.095 ns crc_result\[3\]~789 2 COMB LAB_X27_Y22 3 " "Info: 2: + IC(0.636 ns) + CELL(0.459 ns) = 1.095 ns; Loc. = LAB_X27_Y22; Fanout = 3; COMB Node = 'crc_result\[3\]~789'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "1.095 ns" { crc_result_reg[17] crc_result[3]~789 } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.858 ns) + CELL(0.364 ns) 2.317 ns crc_result_reg\[24\] 3 REG LAB_X22_Y22 11 " "Info: 3: + IC(0.858 ns) + CELL(0.364 ns) = 2.317 ns; Loc. = LAB_X22_Y22; Fanout = 11; REG Node = 'crc_result_reg\[24\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "1.222 ns" { crc_result[3]~789 crc_result_reg[24] } "NODE_NAME" } "" } } { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.823 ns ( 35.52 % ) " "Info: Total cell delay = 0.823 ns ( 35.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns ( 64.48 % ) " "Info: Total interconnect delay = 1.494 ns ( 64.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "2.317 ns" { crc_result_reg[17] crc_result[3]~789 crc_result_reg[24] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 03 15:20:28 2006 " "Info: Processing ended: Fri Mar 03 15:20:28 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Info: Elapsed time: 00:00:23" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}