djs.vhdl

来自「四人抢答器的实现」· VHDL 代码 · 共 43 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
--实现答题倒计时,在计满100S后送出声音提示
entity djs2 is
    Port ( clk,en : in std_logic;
           h,l : out std_logic_vector(3 downto 0);
           sound : out std_logic);
end djs2;

architecture Behavioral of djs2 is

begin
   process(clk,en)
   variable hh,ll:std_logic_vector(3 downto 0);
   begin
      if clk'event and clk='1' then
	    if en='0'then
		    h<=hh;
	         l<=ll;
	      if ll=0 and hh=0 then
		    sound<='1';
		 elsif ll=0 then
		    ll:="1001";
		    hh:=hh-1;
		 else
		    ll:=ll-1;
		 end if;
	    else
	      sound<='0';
		 hh:="1001";
		 ll:="1001";
	    end if;
	 end if;
   end process;
end Behavioral;