qdkz.vhf

四人抢答器的实现

-- VHDL model created from qdkz.sch - Tue Apr 24 09:34:42 2007


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity qdkz is
   port ( clk : in    std_logic; 
          clr : in    std_logic; 
          d1  : in    std_logic; 
          d2  : in    std_logic; 
          d3  : in    std_logic; 
          d4  : in    std_logic; 
          en  : in    std_logic; 
          alm : out   std_logic; 
          q   : out   std_logic_vector (7 downto 0); 
          wx  : out   std_logic_vector (7 downto 0));
end qdkz;

architecture BEHAVIORAL of qdkz is
   attribute BOX_TYPE   : STRING ;
   signal XLXN_1  : std_logic;
   signal XLXN_2  : std_logic_vector (2 downto 0);
   signal XLXN_3  : std_logic_vector (3 downto 0);
   signal XLXN_11 : std_logic;
   signal XLXN_18 : std_logic;
   signal XLXN_20 : std_logic;
   signal XLXN_21 : std_logic;
   signal XLXN_22 : std_logic;
   signal XLXN_23 : std_logic;
   signal XLXN_27 : std_logic;
   signal XLXN_30 : std_logic;
   signal XLXN_40 : std_logic_vector (3 downto 0);
   signal XLXN_41 : std_logic_vector (3 downto 0);
   signal XLXN_42 : std_logic_vector (3 downto 0);
   signal XLXN_50 : std_logic;
   signal XLXN_51 : std_logic;
   signal XLXN_52 : std_logic;
   component ch41a
      port ( d1 : in    std_logic; 
             d2 : in    std_logic; 
             d3 : in    std_logic; 
             d4 : in    std_logic; 
             q  : out   std_logic_vector (3 downto 0));
   end component;
   
   component djs2
      port ( clk   : in    std_logic; 
             en    : in    std_logic; 
             sound : out   std_logic; 
             h     : out   std_logic_vector (3 downto 0); 
             l     : out   std_logic_vector (3 downto 0));
   end component;
   
   component f01ms
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
   component feng1
      port ( cp  : in    std_logic; 
             clr : in    std_logic; 
             q   : out   std_logic);
   end component;
   
   component fpq1s
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
   component lock
      port ( d1  : in    std_logic; 
             d2  : in    std_logic; 
             d3  : in    std_logic; 
             d4  : in    std_logic; 
             clk : in    std_logic; 
             clr : in    std_logic; 
             q1  : out   std_logic; 
             q2  : out   std_logic; 
             q3  : out   std_logic; 
             q4  : out   std_logic; 
             alm : out   std_logic);
   end component;
   
   component sel
      port ( clk : in    std_logic; 
             a   : out   std_logic_vector (2 downto 0));
   end component;
   
   component xzq3
      port ( sel : in    std_logic_vector (2 downto 0); 
             d1  : in    std_logic_vector (3 downto 0); 
             d2  : in    std_logic_vector (3 downto 0); 
             d3  : in    std_logic_vector (3 downto 0); 
             wx  : out   std_logic_vector (7 downto 0); 
             q   : out   std_logic_vector (3 downto 0));
   end component;
   
   component ymq
      port ( A : in    std_logic_vector (3 downto 0); 
             Q : out   std_logic_vector (7 downto 0));
   end component;
   
   component AND4
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND4 : COMPONENT is "BLACK_BOX";
   
   component NOR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of NOR2 : COMPONENT is "BLACK_BOX";
   
   component d
      port ( clk : in    std_logic; 
             d   : in    std_logic; 
             q   : out   std_logic);
   end component;
   
begin
   XLXI_1 : ch41a
      port map (d1=>XLXN_20, d2=>XLXN_21, d3=>XLXN_22, d4=>XLXN_23, q(3 downto
            0)=>XLXN_40(3 downto 0));
   
   XLXI_2 : djs2
      port map (clk=>XLXN_27, en=>en, h(3 downto 0)=>XLXN_41(3 downto 0), l(3
            downto 0)=>XLXN_42(3 downto 0), sound=>XLXN_50);
   
   XLXI_3 : f01ms
      port map (CLK=>clk, CP=>XLXN_1);
   
   XLXI_4 : feng1
      port map (clr=>clr, cp=>XLXN_18, q=>XLXN_11);
   
   XLXI_5 : fpq1s
      port map (CLK=>clk, CP=>XLXN_27);
   
   XLXI_6 : lock
      port map (clk=>XLXN_11, clr=>clr, d1=>d1, d2=>d2, d3=>d3, d4=>d4,
            alm=>XLXN_51, q1=>XLXN_20, q2=>XLXN_21, q3=>XLXN_22, q4=>XLXN_23);
   
   XLXI_7 : sel
      port map (clk=>XLXN_1, a(2 downto 0)=>XLXN_2(2 downto 0));
   
   XLXI_8 : xzq3
      port map (d1(3 downto 0)=>XLXN_41(3 downto 0), d2(3 downto 0)=>XLXN_42(3
            downto 0), d3(3 downto 0)=>XLXN_40(3 downto 0), sel(2 downto
            0)=>XLXN_2(2 downto 0), q(3 downto 0)=>XLXN_3(3 downto 0), wx(7
            downto 0)=>wx(7 downto 0));
   
   XLXI_9 : ymq
      port map (A(3 downto 0)=>XLXN_3(3 downto 0), Q(7 downto 0)=>q(7 downto
            0));
   
   XLXI_25 : AND4
      port map (I0=>d4, I1=>d3, I2=>d2, I3=>d1, O=>XLXN_18);
   
   XLXI_34 : NOR2
      port map (I0=>XLXN_30, I1=>XLXN_52, O=>alm);
   
   XLXI_47 : d
      port map (clk=>XLXN_27, d=>XLXN_50, q=>XLXN_52);
   
   XLXI_48 : d
      port map (clk=>XLXN_27, d=>XLXN_51, q=>XLXN_30);
   
end BEHAVIORAL;