__projnav.log

四人抢答器的实现

Selected Device : 2s50tq144-6 

 Number of Slices:                      14  out of    768     1%  
 Number of Slice Flip Flops:            19  out of   1536     1%  
 Number of 4 input LUTs:                19  out of   1536     1%  
 Number of bonded IOBs:                 16  out of     96    16%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XST_GND:G                          | NONE                   | 2     |
XLXN_43                            | BUFGP                  | 4     |
XLXI_3_q:Q                         | NONE                   | 5     |
XLXI_6__n0001(XLXI_6__n00011:O)    | NONE(*)(XLXI_6_Q_0)    | 7     |
XLXN_13(XLXI_10:O)                 | NONE(*)(XLXI_3_q)      | 1     |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 4.188ns (Maximum Frequency: 238.777MHz)
   Minimum input arrival time before clock: 2.691ns
   Maximum output required time after clock: 11.837ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\wait316\qiangdaqi4ren/_ngo -uc
yingjiao.ucf -p xc2s50-tq144-6 qiangdaqi.ngc qiangdaqi.ngd 

Reading NGO file "E:/VHDL/wait316/qiangdaqi4ren/qiangdaqi.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yingjiao.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:479 - The input pad net 'd4' is driving one or more clock loads
   that should only use a dedicated clock buffer. This could result in large
   clock skews on this net. Check whether the correct type of BUF is being used
   to drive the clock buffer.

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Total memory usage is 39140 kilobytes

Writing NGD file "qiangdaqi.ngd" ...

Writing NGDBUILD log file "qiangdaqi.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\wait316\qiangdaqi4ren/_ngo -uc
yingjiao.ucf -p xc2s50-tq144-6 qiangdaqi.ngc qiangdaqi.ngd 

Reading NGO file "E:/VHDL/wait316/qiangdaqi4ren/qiangdaqi.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yingjiao.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:479 - The input pad net 'd4' is driving one or more clock loads
   that should only use a dedicated clock buffer. This could result in large
   clock skews on this net. Check whether the correct type of BUF is being used
   to drive the clock buffer.

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Total memory usage is 41188 kilobytes

Writing NGD file "qiangdaqi.ngd" ...

Writing NGDBUILD log file "qiangdaqi.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50tq144-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         4 out of  1,536    1%
  Number of 4 input LUTs:            19 out of  1,536    1%
Logic Distribution:
    Number of occupied Slices:                          12 out of    768    1%
    Number of Slices containing only related logic:     12 out of     12  100%
    Number of Slices containing unrelated logic:         0 out of     12    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:        19 out of  1,536    1%
   Number of bonded IOBs:            16 out of     92   17%
      IOB Flip Flops:                               6
      IOB Latches:                                  7
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  229
Additional JTAG gate count for IOBs:  816
Peak Memory Usage:  58 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "qiangdaqi_map.mrp" for details.
Completed process "Map".

Mapping Module qiangdaqi . . .
MAP command line:
map -intstyle ise -p xc2s50-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o qiangdaqi_map.ncd qiangdaqi.ngd qiangdaqi.pcf
Mapping Module qiangdaqi: DONE



Started process "Place & Route".





Constraints file: qiangdaqi.pcf
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 57
   days, this program will not operate. For more information about thisproduct,
   please refer to the Evaluation Agreement, which was shipped toyou along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact yourlocal
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to:[e-mail]
   Thank You!

Loading device database for application Par from file "qiangdaqi_map.ncd".
   "qiangdaqi" is an NCD, version 2.38, device xc2s50, package tq144, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            16 out of 92     17%
      Number of LOCed External IOBs   15 out of 16     93%

   Number of SLICEs                   12 out of 768     1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896f7) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:98f43f) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file qiangdaqi.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 106 unrouted;       REAL time: 0 secs 

Phase 2: 93 unrouted;       REAL time: 0 secs 

Phase 3: 24 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|     XLXN_43_BUFGP          |  Global  |    3   |  0.007     |  0.380      |
+----------------------------+----------+--------+------------+-------------+
|          XLXI_3_q          |Low-Skew  |    5   |  1.520     |  3.990      |
+----------------------------+----------+--------+------------+-------------+
|     XLXI_6__n0001          |   Local  |    7   |  0.188     |  2.707      |
+----------------------------+----------+--------+------------+-------------+
|           XLXN_13          |   Local  |    1   |  0.000     |  0.572      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  49 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file qiangdaqi.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sat Mar 17 19:11:01 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module qiangdaqi . . .
PAR command line: par -w -intstyle ise -ol std -t 1 qiangdaqi_map.ncd qiangdaqi.ncd qiangdaqi.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

WARNING:HDLParsers:3215 - Unit work/FENG is now defined in a different file: was
   E:/VHDL/wait316/qiangdaqi4ren/feng.vhdl, now is E:/qiangdaqi4ren/feng.vhdl
WARNING:HDLParsers:3215 - Unit work/FENG/BEHAVIORAL is now defined in a
   different file: was E:/VHDL/wait316