__projnav.log

四人抢答器的实现

*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      14  out of    768     1%  
 Number of Slice Flip Flops:            19  out of   1536     1%  
 Number of 4 input LUTs:                19  out of   1536     1%  
 Number of bonded IOBs:                 16  out of     96    16%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XST_GND:G                          | NONE                   | 2     |
XLXN_43                            | BUFGP                  | 4     |
XLXI_3_q:Q                         | NONE                   | 5     |
XLXI_6__n0001(XLXI_6__n00011:O)    | NONE(*)(XLXI_6_Q_0)    | 7     |
XLXN_13(XLXI_10:O)                 | NONE(*)(XLXI_3_q)      | 1     |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 4.188ns (Maximum Frequency: 238.777MHz)
   Minimum input arrival time before clock: 2.691ns
   Maximum output required time after clock: 11.837ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\wait316\qiangdaqi4ren/_ngo -uc
yingjiao.ucf -p xc2s50-tq144-6 qiangdaqi.ngc qiangdaqi.ngd 

Reading NGO file "E:/VHDL/wait316/qiangdaqi4ren/qiangdaqi.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yingjiao.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:479 - The input pad net 'd4' is driving one or more clock loads
   that should only use a dedicated clock buffer. This could result in large
   clock skews on this net. Check whether the correct type of BUF is being used
   to drive the clock buffer.

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Total memory usage is 39140 kilobytes

Writing NGD file "qiangdaqi.ngd" ...

Writing NGDBUILD log file "qiangdaqi.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
WARNING:DesignEntry:11 - Net "XLXN_27" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
WARNING:DesignEntry:13 - Net "clk1" is connected to source pins and/or IO ports
   while there is no load pin connected to it
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 57
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/ch41a.vhdl in Library work.
Architecture behavioral of Entity ch41a is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/djs.vhdl in Library work.
Architecture behavioral of Entity djs is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/feng.vhdl in Library work.
Entity <feng> (Architecture <behavioral>) compiled.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/lock.vhdl in Library work.
Architecture behavioral of Entity lock is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/sel.vhdl in Library work.
Architecture behavioral of Entity sel is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/ymq.vhdl in Library work.
Architecture behavioral of Entity ymq is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/xzq3_1.vhdl in Library work.
Architecture behavioral of Entity xzq3_1 is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/fpq2ms.vhdl in Library work.
Architecture behavioral of Entity fpq2ms is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/fpq1s.vhdl in Library work.
Architecture behavioral of Entity fpq1s is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/qiangdaqi.vhf in Library work.
Entity <qiangdaqi> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <qiangdaqi> (Architecture <behavioral>).
    Set user-defined property "INIT =  0" for unit <LDCP>.
    Set user-defined property "INIT =  0" for unit <LDCP>.
Entity <qiangdaqi> analyzed. Unit <qiangdaqi> generated.

Analyzing Entity <ch41a> (Architecture <behavioral>).
Entity <ch41a> analyzed. Unit <ch41a> generated.

Analyzing Entity <djs> (Architecture <behavioral>).
Entity <djs> analyzed. Unit <djs> generated.

Analyzing Entity <feng> (Architecture <behavioral>).
Entity <feng> analyzed. Unit <feng> generated.

Analyzing Entity <lock> (Architecture <behavioral>).
WARNING:Xst:819 - E:/VHDL/wait316/qiangdaqi4ren/lock.vhdl line 20: The following signals are missing in the process sensitivity list:
   clr.
Entity <lock> analyzed. Unit <lock> generated.

Analyzing Entity <sel> (Architecture <behavioral>).
Entity <sel> analyzed. Unit <sel> generated.

Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.

Analyzing Entity <xzq3_1> (Architecture <behavioral>).
Entity <xzq3_1> analyzed. Unit <xzq3_1> generated.

Analyzing Entity <fpq2ms> (Architecture <behavioral>).
Entity <fpq2ms> analyzed. Unit <fpq2ms> generated.

Analyzing Entity <fpq1s> (Architecture <behavioral>).
Entity <fpq1s> analyzed. Unit <fpq1s> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpq1s>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/fpq1s.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 24-bit comparator lessequal for signal <$n0002>.
    Found 24-bit comparator greatequal for signal <$n0007>.
    Found 24-bit comparator lessequal for signal <$n0008>.
    Found 24-bit up counter for signal <count>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq1s> synthesized.


Synthesizing Unit <fpq2ms>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/fpq2ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 15-bit comparator lessequal for signal <$n0002>.
    Found 15-bit comparator greatequal for signal <$n0007>.
    Found 15-bit comparator lessequal for signal <$n0008>.
    Found 15-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq2ms> synthesized.


Synthesizing Unit <xzq3_1>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/xzq3_1.vhdl.
Unit <xzq3_1> synthesized.


Synthesizing Unit <ymq>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/ymq.vhdl.
WARNING:Xst:737 - Found 7-bit latch for signal <Q>.
Unit <ymq> synthesized.


Synthesizing Unit <sel>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/sel.vhdl.
    Found 3-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <sel> synthesized.


Synthesizing Unit <lock>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/lock.vhdl.
    Found 1-bit register for signal <q1>.
    Found 1-bit register for signal <q2>.
    Found 1-bit register for signal <q3>.
    Found 1-bit register for signal <q4>.
    Found 1-bit register for signal <alm>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <lock> synthesized.


Synthesizing Unit <feng>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/feng.vhdl.
    Found 1-bit register for signal <q>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <feng> synthesized.


Synthesizing Unit <djs>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/djs.vhdl.
    Found 1-bit register for signal <sound>.
    Found 4-bit down counter for signal <hh>.
    Found 4-bit down counter for signal <ll>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <djs> synthesized.


Synthesizing Unit <ch41a>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/ch41a.vhdl.
Unit <ch41a> synthesized.


Synthesizing Unit <qiangdaqi>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/qiangdaqi.vhf.
WARNING:Xst:653 - Signal <XLXN_27> is used but never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <clk1_DUMMY> is assigned but never used.
Unit <qiangdaqi> synthesized.

WARNING:Xst:524 - All outputs of the instance <XLXI_33> of the block <fpq1s> are unconnected in block <qiangdaqi>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <XLXI_32> of the block <fpq2ms> are unconnected in block <qiangdaqi>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 3
 4-bit down counter                : 2
 3-bit up counter                  : 1
# Registers                        : 7
 1-bit register                    : 7
# Latches                          : 1
 7-bit latch                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <qiangdaqi> ...

Optimizing unit <ch41a> ...

Optimizing unit <xzq3_1> ...

Optimizing unit <ymq> ...

Optimizing unit <fpq2ms> ...

Optimizing unit <fpq1s> ...

Optimizing unit <djs> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1710 - FF/Latch  <XLXI_2_sound> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_hh_1> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_ll_1> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_hh_3> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_hh_2> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_hh_0> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_ll_3> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_ll_2> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_ll_0> (without init value) is constant in block <qiangdaqi>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block qiangdaqi, actual ratio is 1.
FlipFlop XLXI_5_cnt_0 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------