__projnav.log

四人抢答器的实现

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  48 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file qiangdaqi.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Mar 16 21:20:13 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module qiangdaqi . . .
PAR command line: par -w -intstyle ise -ol std -t 1 qiangdaqi_map.ncd qiangdaqi.ncd qiangdaqi.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
WARNING:DesignEntry:11 - Net "XLXN_27" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
WARNING:DesignEntry:13 - Net "clk" is connected to source pins and/or IO ports
   while there is no load pin connected to it
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 57
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/QIANGDAQI is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/qiangdaqi.vhf, now is E:/VHDL/wait316/qiangdaqi4ren/qiangdaqi.vhf
WARNING:HDLParsers:3215 - Unit work/QIANGDAQI/BEHAVIORAL is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/qiangdaqi.vhf, now is E:/VHDL/wait316/qiangdaqi4ren/qiangdaqi.vhf
WARNING:HDLParsers:3215 - Unit work/FPQ1S is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/fpq1s.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/fpq1s.vhdl
WARNING:HDLParsers:3215 - Unit work/FPQ1S/BEHAVIORAL is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/fpq1s.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/fpq1s.vhdl
WARNING:HDLParsers:3215 - Unit work/FPQ2MS is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/fpq2ms.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/fpq2ms.vhdl
WARNING:HDLParsers:3215 - Unit work/FPQ2MS/BEHAVIORAL is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/fpq2ms.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/fpq2ms.vhdl
WARNING:HDLParsers:3215 - Unit work/XZQ3_1 is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/xzq3_1.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/xzq3_1.vhdl
WARNING:HDLParsers:3215 - Unit work/XZQ3_1/BEHAVIORAL is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/xzq3_1.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/xzq3_1.vhdl
WARNING:HDLParsers:3215 - Unit work/YMQ is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/ymq.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/ymq.vhdl
WARNING:HDLParsers:3215 - Unit work/YMQ/BEHAVIORAL is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/ymq.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/ymq.vhdl
WARNING:HDLParsers:3215 - Unit work/SEL is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/sel.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/sel.vhdl
WARNING:HDLParsers:3215 - Unit work/SEL/BEHAVIORAL is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/sel.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/sel.vhdl
WARNING:HDLParsers:3215 - Unit work/LOCK is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/lock.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/lock.vhdl
WARNING:HDLParsers:3215 - Unit work/LOCK/BEHAVIORAL is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/lock.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/lock.vhdl
WARNING:HDLParsers:3215 - Unit work/FENG is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/feng.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/feng.vhdl
WARNING:HDLParsers:3215 - Unit work/FENG/BEHAVIORAL is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/feng.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/feng.vhdl
WARNING:HDLParsers:3215 - Unit work/DJS is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/djs.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/djs.vhdl
WARNING:HDLParsers:3215 - Unit work/DJS/BEHAVIORAL is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/djs.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/djs.vhdl
WARNING:HDLParsers:3215 - Unit work/CH41A is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/ch41a.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/ch41a.vhdl
WARNING:HDLParsers:3215 - Unit work/CH41A/BEHAVIORAL is now defined in a different file: was e:/vhdl/test_12jiao/qiangdaqi4ren/ch41a.vhdl, now is E:/VHDL/wait316/qiangdaqi4ren/ch41a.vhdl
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/ch41a.vhdl in Library work.
Architecture behavioral of Entity ch41a is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/djs.vhdl in Library work.
Architecture behavioral of Entity djs is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/feng.vhdl in Library work.
Architecture behavioral of Entity feng is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/lock.vhdl in Library work.
Architecture behavioral of Entity lock is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/sel.vhdl in Library work.
Architecture behavioral of Entity sel is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/ymq.vhdl in Library work.
Architecture behavioral of Entity ymq is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/xzq3_1.vhdl in Library work.
Architecture behavioral of Entity xzq3_1 is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/fpq2ms.vhdl in Library work.
Architecture behavioral of Entity fpq2ms is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/fpq1s.vhdl in Library work.
Architecture behavioral of Entity fpq1s is up to date.
Compiling vhdl file E:/VHDL/wait316/qiangdaqi4ren/qiangdaqi.vhf in Library work.
Entity <qiangdaqi> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <qiangdaqi> (Architecture <behavioral>).
    Set user-defined property "INIT =  0" for unit <LDCP>.
    Set user-defined property "INIT =  0" for unit <LDCP>.
Entity <qiangdaqi> analyzed. Unit <qiangdaqi> generated.

Analyzing Entity <ch41a> (Architecture <behavioral>).
Entity <ch41a> analyzed. Unit <ch41a> generated.

Analyzing Entity <djs> (Architecture <behavioral>).
Entity <djs> analyzed. Unit <djs> generated.

Analyzing Entity <feng> (Architecture <behavioral>).
Entity <feng> analyzed. Unit <feng> generated.

Analyzing Entity <lock> (Architecture <behavioral>).
WARNING:Xst:819 - E:/VHDL/wait316/qiangdaqi4ren/lock.vhdl line 20: The following signals are missing in the process sensitivity list:
   clr.
Entity <lock> analyzed. Unit <lock> generated.

Analyzing Entity <sel> (Architecture <behavioral>).
Entity <sel> analyzed. Unit <sel> generated.

Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.

Analyzing Entity <xzq3_1> (Architecture <behavioral>).
Entity <xzq3_1> analyzed. Unit <xzq3_1> generated.

Analyzing Entity <fpq2ms> (Architecture <behavioral>).
Entity <fpq2ms> analyzed. Unit <fpq2ms> generated.

Analyzing Entity <fpq1s> (Architecture <behavioral>).
Entity <fpq1s> analyzed. Unit <fpq1s> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpq1s>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/fpq1s.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 24-bit comparator lessequal for signal <$n0002>.
    Found 24-bit comparator greatequal for signal <$n0007>.
    Found 24-bit comparator lessequal for signal <$n0008>.
    Found 24-bit up counter for signal <count>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq1s> synthesized.


Synthesizing Unit <fpq2ms>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/fpq2ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 15-bit comparator lessequal for signal <$n0002>.
    Found 15-bit comparator greatequal for signal <$n0007>.
    Found 15-bit comparator lessequal for signal <$n0008>.
    Found 15-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq2ms> synthesized.


Synthesizing Unit <xzq3_1>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/xzq3_1.vhdl.
Unit <xzq3_1> synthesized.


Synthesizing Unit <ymq>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/ymq.vhdl.
WARNING:Xst:737 - Found 7-bit latch for signal <Q>.
Unit <ymq> synthesized.


Synthesizing Unit <sel>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/sel.vhdl.
    Found 3-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <sel> synthesized.


Synthesizing Unit <lock>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/lock.vhdl.
    Found 1-bit register for signal <q1>.
    Found 1-bit register for signal <q2>.
    Found 1-bit register for signal <q3>.
    Found 1-bit register for signal <q4>.
    Found 1-bit register for signal <alm>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <lock> synthesized.


Synthesizing Unit <feng>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/feng.vhdl.
    Found 1-bit register for signal <q>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <feng> synthesized.


Synthesizing Unit <djs>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/djs.vhdl.
    Found 1-bit register for signal <sound>.
    Found 4-bit down counter for signal <hh>.
    Found 4-bit down counter for signal <ll>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <djs> synthesized.


Synthesizing Unit <ch41a>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/ch41a.vhdl.
Unit <ch41a> synthesized.


Synthesizing Unit <qiangdaqi>.
    Related source file is E:/VHDL/wait316/qiangdaqi4ren/qiangdaqi.vhf.
WARNING:Xst:653 - Signal <XLXN_27> is used but never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <clk_DUMMY> is assigned but never used.
Unit <qiangdaqi> synthesized.

WARNING:Xst:524 - All outputs of the instance <XLXI_33> of the block <fpq1s> are unconnected in block <qiangdaqi>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <XLXI_32> of the block <fpq2ms> are unconnected in block <qiangdaqi>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 3
 4-bit down counter                : 2
 3-bit up counter                  : 1
# Registers                        : 7
 1-bit register                    : 7
# Latches                          : 1
 7-bit latch                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <qiangdaqi> ...

Optimizing unit <ch41a> ...

Optimizing unit <xzq3_1> ...

Optimizing unit <ymq> ...

Optimizing unit <fpq2ms> ...

Optimizing unit <fpq1s> ...

Optimizing unit <djs> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1710 - FF/Latch  <XLXI_2_sound> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_hh_1> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_ll_1> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_hh_3> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_hh_2> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_hh_0> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_ll_3> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_ll_2> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_ll_0> (without init value) is constant in block <qiangdaqi>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block qiangdaqi, actual ratio is 1.
FlipFlop XLXI_5_cnt_0 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================