__projnav.log

四人抢答器的实现

Synthesizing Unit <lock>.
    Related source file is e:/vhdl/test_12jiao/qiangdaqi4ren/lock.vhdl.
    Found 1-bit register for signal <q1>.
    Found 1-bit register for signal <q2>.
    Found 1-bit register for signal <q3>.
    Found 1-bit register for signal <q4>.
    Found 1-bit register for signal <alm>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <lock> synthesized.


Synthesizing Unit <feng>.
    Related source file is e:/vhdl/test_12jiao/qiangdaqi4ren/feng.vhdl.
    Found 1-bit register for signal <q>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <feng> synthesized.


Synthesizing Unit <djs>.
    Related source file is e:/vhdl/test_12jiao/qiangdaqi4ren/djs.vhdl.
    Found 1-bit register for signal <sound>.
    Found 4-bit down counter for signal <hh>.
    Found 4-bit down counter for signal <ll>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <djs> synthesized.


Synthesizing Unit <ch41a>.
    Related source file is e:/vhdl/test_12jiao/qiangdaqi4ren/ch41a.vhdl.
Unit <ch41a> synthesized.


Synthesizing Unit <qiangdaqi>.
    Related source file is e:/vhdl/test_12jiao/qiangdaqi4ren/qiangdaqi.vhf.
WARNING:Xst:653 - Signal <XLXN_12> is used but never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <XLXN_27> is used but never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <clk_DUMMY> is assigned but never used.
Unit <qiangdaqi> synthesized.

WARNING:Xst:524 - All outputs of the instance <XLXI_33> of the block <fpq1s> are unconnected in block <qiangdaqi>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <XLXI_32> of the block <fpq2ms> are unconnected in block <qiangdaqi>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 3
 4-bit down counter                : 2
 3-bit up counter                  : 1
# Registers                        : 7
 1-bit register                    : 7
# Latches                          : 1
 7-bit latch                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <qiangdaqi> ...

Optimizing unit <ch41a> ...

Optimizing unit <xzq3_1> ...

Optimizing unit <ymq> ...

Optimizing unit <fpq2ms> ...

Optimizing unit <fpq1s> ...

Optimizing unit <djs> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1710 - FF/Latch  <XLXI_2_sound> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_hh_1> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_ll_1> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_hh_3> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_hh_2> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_hh_0> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_ll_3> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_ll_2> (without init value) is constant in block <qiangdaqi>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_ll_0> (without init value) is constant in block <qiangdaqi>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block qiangdaqi, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      13  out of    768     1%  
 Number of Slice Flip Flops:            18  out of   1536     1%  
 Number of 4 input LUTs:                18  out of   1536     1%  
 Number of bonded IOBs:                 12  out of     96    12%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XST_GND:G                          | NONE                   | 2     |
XLXN_43                            | BUFGP                  | 3     |
XLXI_3_q:Q                         | NONE                   | 5     |
XLXI_6__n0001(XLXI_6__n00011:O)    | NONE(*)(XLXI_6_Q_2)    | 7     |
XLXN_13(XLXI_10:O)                 | NONE(*)(XLXI_3_q)      | 1     |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 4.098ns (Maximum Frequency: 244.021MHz)
   Minimum input arrival time before clock: 2.691ns
   Maximum output required time after clock: 11.837ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\test_12jiao\qiangdaqi4ren/_ngo
-i -p xc2s50-tq144-6 qiangdaqi.ngc qiangdaqi.ngd 

Reading NGO file "e:/vhdl/test_12jiao/qiangdaqi4ren/qiangdaqi.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:479 - The input pad net 'd4' is driving one or more clock loads
   that should only use a dedicated clock buffer. This could result in large
   clock skews on this net. Check whether the correct type of BUF is being used
   to drive the clock buffer.

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Total memory usage is 39140 kilobytes

Writing NGD file "qiangdaqi.ngd" ...

Writing NGDBUILD log file "qiangdaqi.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50tq144-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:         3 out of  1,536    1%
  Number of 4 input LUTs:             8 out of  1,536    1%
Logic Distribution:
    Number of occupied Slices:                           5 out of    768    1%
    Number of Slices containing only related logic:      5 out of      5  100%
    Number of Slices containing unrelated logic:         0 out of      5    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         8 out of  1,536    1%
   Number of bonded IOBs:             8 out of     92    8%
      IOB Latches:                                  5
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  97
Additional JTAG gate count for IOBs:  432
Peak Memory Usage:  58 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "qiangdaqi_map.mrp" for details.
Completed process "Map".

Mapping Module qiangdaqi . . .
MAP command line:
map -intstyle ise -p xc2s50-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o qiangdaqi_map.ncd qiangdaqi.ngd qiangdaqi.pcf
Mapping Module qiangdaqi: DONE



Started process "Place & Route".





Constraints file: qiangdaqi.pcf
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 58
   days, this program will not operate. For more information about thisproduct,
   please refer to the Evaluation Agreement, which was shipped toyou along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact yourlocal
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to:[e-mail]
   Thank You!

Loading device database for application Par from file "qiangdaqi_map.ncd".
   "qiangdaqi" is an NCD, version 2.38, device xc2s50, package tq144, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             8 out of 92      8%
      Number of LOCed External IOBs    0 out of 8       0%

   Number of SLICEs                    5 out of 768     1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896bb) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:98a4da) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file qiangdaqi.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 31 unrouted;       REAL time: 0 secs 

Phase 2: 25 unrouted;       REAL time: 0 secs 

Phase 3: 5 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|     XLXN_43_BUFGP          |  Global  |    2   |  0.001     |  0.376      |
+----------------------------+----------+--------+------------+-------------+
|     XLXI_6__n0001          |Low-Skew  |    5   |  0.119     |  2.909      |
+----------------------------+----------+--------+------------+-------------+