__projnav.log

四人抢答器的实现

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Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/sel.vhdl in Library work.
Entity <sel> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/lock.vhdl in Library work.
Entity <lock> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/ch41a.vhdl in Library
work.
Entity <ch41a> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/djs.vhdl in Library work.
Entity <djs> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/ymq.vhdl in Library work.
Entity <YMQ> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/feng.vhdl in Library work.
Entity <feng> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/xzq3_1.vhdl in Library
work.
Entity <xzq3_1> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/fpq2ms.vhdl in Library
work.
Entity <fpq2ms> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/fpq1s.vhdl in Library
work.
Entity <fpq1S> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
WARNING:DesignEntry:11 - Net "XLXN_12" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
WARNING:DesignEntry:11 - Net "XLXN_27" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
WARNING:DesignEntry:13 - Net "clk" is connected to source pins and/or IO ports
   while there is no load pin connected to it
ERROR:DesignEntry:20 - Pin "h(3:0)" is connected to a bus of a different width.
ERROR:DesignEntry:20 - Pin "d2(3:0)" is connected to a bus of a different width.
Error: 
Process "View VHDL Functional Model" did not complete.


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Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
WARNING:DesignEntry:11 - Net "XLXN_12" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
WARNING:DesignEntry:11 - Net "XLXN_27" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
WARNING:DesignEntry:13 - Net "clk" is connected to source pins and/or IO ports
   while there is no load pin connected to it
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 58
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/ch41a.vhdl in Library work.
Entity <ch41a> (Architecture <behavioral>) compiled.
Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/djs.vhdl in Library work.
Entity <djs> (Architecture <behavioral>) compiled.
Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/feng.vhdl in Library work.
Architecture behavioral of Entity feng is up to date.
Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/lock.vhdl in Library work.
Entity <lock> (Architecture <behavioral>) compiled.
Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/sel.vhdl in Library work.
Architecture behavioral of Entity sel is up to date.
Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/ymq.vhdl in Library work.
Architecture behavioral of Entity ymq is up to date.
Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/xzq3_1.vhdl in Library work.
Architecture behavioral of Entity xzq3_1 is up to date.
Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/fpq2ms.vhdl in Library work.
Architecture behavioral of Entity fpq2ms is up to date.
Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/fpq1s.vhdl in Library work.
Architecture behavioral of Entity fpq1s is up to date.
Compiling vhdl file e:/vhdl/test_12jiao/qiangdaqi4ren/qiangdaqi.vhf in Library work.
Entity <qiangdaqi> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <qiangdaqi> (Architecture <BEHAVIORAL>).
    Set user-defined property "INIT =  0" for unit <LDCP>.
    Set user-defined property "INIT =  0" for unit <LDCP>.
Entity <qiangdaqi> analyzed. Unit <qiangdaqi> generated.

Analyzing Entity <ch41a> (Architecture <behavioral>).
Entity <ch41a> analyzed. Unit <ch41a> generated.

Analyzing Entity <djs> (Architecture <behavioral>).
Entity <djs> analyzed. Unit <djs> generated.

Analyzing Entity <feng> (Architecture <behavioral>).
Entity <feng> analyzed. Unit <feng> generated.

Analyzing Entity <lock> (Architecture <behavioral>).
WARNING:Xst:819 - e:/vhdl/test_12jiao/qiangdaqi4ren/lock.vhdl line 20: The following signals are missing in the process sensitivity list:
   clr.
Entity <lock> analyzed. Unit <lock> generated.

Analyzing Entity <sel> (Architecture <behavioral>).
Entity <sel> analyzed. Unit <sel> generated.

Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.

Analyzing Entity <xzq3_1> (Architecture <behavioral>).
Entity <xzq3_1> analyzed. Unit <xzq3_1> generated.

Analyzing Entity <fpq2ms> (Architecture <behavioral>).
Entity <fpq2ms> analyzed. Unit <fpq2ms> generated.

Analyzing Entity <fpq1s> (Architecture <behavioral>).
Entity <fpq1s> analyzed. Unit <fpq1s> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpq1s>.
    Related source file is e:/vhdl/test_12jiao/qiangdaqi4ren/fpq1s.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 24-bit comparator lessequal for signal <$n0002>.
    Found 24-bit comparator greatequal for signal <$n0007>.
    Found 24-bit comparator lessequal for signal <$n0008>.
    Found 24-bit up counter for signal <count>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq1s> synthesized.


Synthesizing Unit <fpq2ms>.
    Related source file is e:/vhdl/test_12jiao/qiangdaqi4ren/fpq2ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 15-bit comparator lessequal for signal <$n0002>.
    Found 15-bit comparator greatequal for signal <$n0007>.
    Found 15-bit comparator lessequal for signal <$n0008>.
    Found 15-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq2ms> synthesized.


Synthesizing Unit <xzq3_1>.
    Related source file is e:/vhdl/test_12jiao/qiangdaqi4ren/xzq3_1.vhdl.
Unit <xzq3_1> synthesized.


Synthesizing Unit <ymq>.
    Related source file is e:/vhdl/test_12jiao/qiangdaqi4ren/ymq.vhdl.
WARNING:Xst:737 - Found 7-bit latch for signal <Q>.
Unit <ymq> synthesized.


Synthesizing Unit <sel>.
    Related source file is e:/vhdl/test_12jiao/qiangdaqi4ren/sel.vhdl.
    Found 3-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <sel> synthesized.