ch41a.vhdl

来自「四人抢答器的实现」· VHDL 代码 · 共 32 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
--将抢答结果转换为二进制数
entity ch41a is
    Port ( d1,d2,d3,d4 : in std_logic;
           q : out std_logic_vector(3 downto 0));
end ch41a;

architecture Behavioral of ch41a is

begin
   process(d1,d2,d3,d4)
   variable tmp:std_logic_vector(3 downto 0);
   begin
	 tmp:=d1&d2&d3&d4;
	 case tmp is 
	     when "0111"=>q<="0001";
		when "1011"=>q<="0010";
	     when "1101"=>q<="0011";
		when "1110"=>q<="0100";
		when others=>q<="1111";
	 end case;
   end process;
end Behavioral;