lock.vhdl

四人抢答器的实现

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
--在任一选手按下按键后锁存,锁存的同时送出ALM信号,实现声音提示
entity lock is
    Port ( d1,d2,d3,d4 : in std_logic;
           clk,clr : in std_logic;
           q1,q2,q3,q4,alm : out std_logic);
end lock;

architecture Behavioral of lock is

begin
   process(clk,d1,d2,d3,d4)
   begin
      if clr='0' then
	    q1<='0';
	    q2<='0';
	    q3<='0';
	    q4<='0';
	    alm<='0';
	 elsif clk'event and clk='1'then
	    q1<=d1;
	    q2<=d2;
	    q3<=d3;
	    q4<=d4;
	    alm<='1';
	 end if;
   end process;
end Behavioral;