xzq3_1.vhdl

来自「四人抢答器的实现」· VHDL 代码 · 共 30 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity xzq3_1 is
    Port ( sel : in std_logic_vector(2 downto 0);
           d1,d2,d3 : in std_logic_vector(3 downto 0);
           q : out std_logic_vector(3 downto 0));
end xzq3_1;

architecture Behavioral of xzq3_1 is

begin
    process(sel,d1,d2,d3)
    begin
       case sel is
	      when"000"=>q<=d1;
		 when"001"=>q<=d2;
		 when"111"=>q<=d3;
		 when others=>q<="1111";
	  end case;
    end process;	   
end Behavioral;