sel.vhdl

来自「四人抢答器的实现」· VHDL 代码 · 共 28 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
--产生片选信号
entity sel is
    Port ( clk : in std_logic;
           a : out std_logic_vector(2 downto 0));
end sel;

architecture Behavioral of sel is

begin
    process(clk)
    variable cnt:std_logic_vector(2 downto 0);
    begin
      if clk'event and clk='1'then
         cnt:=cnt+1;
	 end if;
	    a<=cnt; 
    end process;
end Behavioral;