feng1.vhdl

来自「四人抢答器的实现」· VHDL 代码 · 共 29 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
--此模块在任一个选手按下按键后,输出高电平给锁存器,锁存当时的按键状态.由于没有时钟同步,所以
--锁存的延时时间只是硬件延时时间,从而出现锁存错误的概率接近零.
entity feng1 is
    Port ( cp,clr : in std_logic;
           q : out std_logic);
end feng1;

architecture Behavioral of feng1 is

begin
   process(cp,clr)
   begin
     if clr='0' then
	  q<='0';
     elsif cp'event and cp='0'then
	  q<='1';
	end if;
   end process;
end Behavioral;