d.vhdl

四人抢答器的实现

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity d is
    Port ( clk,d : in std_logic;
           q : out std_logic);
end d;

architecture Behavioral of d is
 signal cnt:std_logic_vector(1 downto 0):="00";
begin
  process(clk)
  begin
     if clk'event and clk='1'then
	 if d='1' then
	  if cnt<"10" then
	      q<='1';
		 cnt<=cnt+1;
	  else
	     cnt<=cnt;
		q<='0';
	  end if;
	 else
	    cnt<="00";
	 end if;
	end if;
  end process;
end Behavioral;