d_chufaqi.vhdl

来自「四人抢答器的实现」· VHDL 代码 · 共 26 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity d_chufaqi is
    Port ( clk,d : in std_logic;
           q : out std_logic);
end d_chufaqi;

architecture Behavioral of d_chufaqi is

begin
  process(clk)
  begin
     if clk'event and clk='1'then
	   q<=d;
	end if;
  end process;
end Behavioral;