qd.par

四人抢答器的实现

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

ZSX-PC::  Thu Mar 29 15:35:05 2007


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 qd_map.ncd qd.ncd qd.pcf


Constraints file: qd.pcf

Loading device database for application Par from file "qd_map.ncd".
   "qd" is an NCD, version 2.38, device xc2s50, package tq144, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolved that IOB <en> must be placed at site P41.
Resolved that GCLKIOB <clk> must be placed at site P88.
Resolved that IOB <clr> must be placed at site P23.
Resolved that IOB <wx<0>> must be placed at site P77.
Resolved that IOB <wx<1>> must be placed at site P78.
Resolved that IOB <wx<2>> must be placed at site P79.
Resolved that IOB <d1> must be placed at site P39.
Resolved that IOB <d2> must be placed at site P31.
Resolved that IOB <d3> must be placed at site P29.
Resolved that IOB <d4> must be placed at site P27.
Resolved that IOB <seg<0>> must be placed at site P58.
Resolved that IOB <seg<1>> must be placed at site P60.
Resolved that IOB <seg<2>> must be placed at site P63.
Resolved that IOB <seg<3>> must be placed at site P65.
Resolved that IOB <seg<4>> must be placed at site P67.
Resolved that IOB <seg<5>> must be placed at site P74.
Resolved that IOB <seg<6>> must be placed at site P75.
Resolved that IOB <sound> must be placed at site P21.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            17 out of 92     18%
      Number of LOCed External IOBs   17 out of 17    100%

   Number of SLICEs                  103 out of 768    13%

   Number of GCLKs                     1 out of 4      25%
   Number of TBUFs                     2 out of 832     1%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9899c3) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
......................................
Phase 5.8 (Checksum:9bde0c) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file qd.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 527 unrouted;       REAL time: 0 secs 

Phase 2: 489 unrouted;       REAL time: 4 secs 

Phase 3: 100 unrouted;       REAL time: 4 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 3 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   24   |  0.070     |  0.465      |
+----------------------------+----------+--------+------------+-------------+
|            XLXN_1          |   Local  |    3   |  0.127     |  1.800      |
+----------------------------+----------+--------+------------+-------------+
|          XLXI_4_q          |   Local  |    5   |  1.597     |  4.112      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_10__n0001          |   Local  |    7   |  0.300     |  2.758      |
+----------------------------+----------+--------+------------+-------------+
|           XLXN_51          |   Local  |    9   |  0.471     |  2.091      |
+----------------------------+----------+--------+------------+-------------+
|           XLXN_22          |   Local  |    1   |  0.000     |  0.573      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 142


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.980
   The MAXIMUM PIN DELAY IS:                               4.112
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.178

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         309         193          21           2           2           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  65 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file qd.ncd.


PAR done.