chw.vhdl

来自「8*8点阵的实现」· VHDL 代码 · 共 34 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity chw is
    Port ( clk : in std_logic;
           q : out std_logic_vector(1 downto 0));
end chw;

architecture Behavioral of chw is

begin
  process(clk)
  variable cnt:integer;
  variable tmp:std_logic_vector(1 downto 0);
  begin
     if clk'event and clk='1'then
	  if cnt<2000 then
	     cnt:=cnt+1;
       else 
	     cnt:=0;
	     tmp:=tmp+1;
	  end if;
	end if;
	q<=tmp;
  end process;
end Behavioral;