__projnav.log

8*8点阵的实现

TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXN_5(XLXI_12_I3_0:O)             | NONE(*)(XLXI_1_cnt_30) | 45    |
clk                                | BUFGP                  | 17    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.228ns (Maximum Frequency: 121.536MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 10.802ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\waitpast\dianzheng/_ngo -uc
yj3.ucf -p xc2s50-tq144-6 dianzheng.ngc dianzheng.ngd 

Reading NGO file "E:/VHDL/waitpast/dianzheng/dianzheng.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yj3.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 52428 kilobytes

Writing NGD file "dianzheng.ngd" ...

Writing NGDBUILD log file "dianzheng.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/DIANZHENG is now defined in a different file: was E:/VHDL/waitpast/dianzheng/dianzheng.vhf, now is E:/zsx/dianzheng/dianzheng.vhf
WARNING:HDLParsers:3215 - Unit work/DIANZHENG/BEHAVIORAL is now defined in a different file: was E:/VHDL/waitpast/dianzheng/dianzheng.vhf, now is E:/zsx/dianzheng/dianzheng.vhf
WARNING:HDLParsers:3215 - Unit work/FPQ2MS is now defined in a different file: was E:/VHDL/waitpast/dianzheng/fpq2ms.vhdl, now is E:/zsx/dianzheng/fpq2ms.vhdl
WARNING:HDLParsers:3215 - Unit work/FPQ2MS/BEHAVIORAL is now defined in a different file: was E:/VHDL/waitpast/dianzheng/fpq2ms.vhdl, now is E:/zsx/dianzheng/fpq2ms.vhdl
WARNING:HDLParsers:3215 - Unit work/HONG_LV is now defined in a different file: was E:/VHDL/waitpast/dianzheng/colour_control.vhdl, now is E:/zsx/dianzheng/colour_control.vhdl
WARNING:HDLParsers:3215 - Unit work/HONG_LV/HONG_LV_ARCH is now defined in a different file: was E:/VHDL/waitpast/dianzheng/colour_control.vhdl, now is E:/zsx/dianzheng/colour_control.vhdl
WARNING:HDLParsers:3215 - Unit work/DZ_SCAN is now defined in a different file: was E:/VHDL/waitpast/dianzheng/lie_scan.vhdl, now is E:/zsx/dianzheng/lie_scan.vhdl
WARNING:HDLParsers:3215 - Unit work/DZ_SCAN/DZ_SCAN_ARCH is now defined in a different file: was E:/VHDL/waitpast/dianzheng/lie_scan.vhdl, now is E:/zsx/dianzheng/lie_scan.vhdl
WARNING:HDLParsers:3215 - Unit work/CONT is now defined in a different file: was E:/VHDL/waitpast/dianzheng/cont.vhdl, now is E:/zsx/dianzheng/cont.vhdl
WARNING:HDLParsers:3215 - Unit work/CONT/BEHAVIORAL is now defined in a different file: was E:/VHDL/waitpast/dianzheng/cont.vhdl, now is E:/zsx/dianzheng/cont.vhdl
WARNING:HDLParsers:3215 - Unit work/CNTA is now defined in a different file: was E:/VHDL/waitpast/dianzheng/cnta.vhdl, now is E:/zsx/dianzheng/cnta.vhdl
WARNING:HDLParsers:3215 - Unit work/CNTA/BEHAVIORAL is now defined in a different file: was E:/VHDL/waitpast/dianzheng/cnta.vhdl, now is E:/zsx/dianzheng/cnta.vhdl
WARNING:HDLParsers:3215 - Unit work/CHW is now defined in a different file: was E:/VHDL/waitpast/dianzheng/chw.vhdl, now is E:/zsx/dianzheng/chw.vhdl
WARNING:HDLParsers:3215 - Unit work/CHW/BEHAVIORAL is now defined in a different file: was E:/VHDL/waitpast/dianzheng/chw.vhdl, now is E:/zsx/dianzheng/chw.vhdl
Compiling vhdl file E:/zsx/dianzheng/chw.vhdl in Library work.
Architecture behavioral of Entity chw is up to date.
Compiling vhdl file E:/zsx/dianzheng/cnta.vhdl in Library work.
Architecture behavioral of Entity cnta is up to date.
Compiling vhdl file E:/zsx/dianzheng/cont.vhdl in Library work.
Entity <cont> (Architecture <behavioral>) compiled.
Compiling vhdl file E:/zsx/dianzheng/lie_scan.vhdl in Library work.
Architecture dz_scan_arch of Entity dz_scan is up to date.
Compiling vhdl file E:/zsx/dianzheng/colour_control.vhdl in Library work.
Architecture hong_lv_arch of Entity hong_lv is up to date.
Compiling vhdl file E:/zsx/dianzheng/fpq2ms.vhdl in Library work.
Architecture behavioral of Entity fpq2ms is up to date.
Compiling vhdl file E:/zsx/dianzheng/dianzheng.vhf in Library work.
Architecture behavioral of Entity dianzheng is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <dianzheng> (Architecture <behavioral>).
Entity <dianzheng> analyzed. Unit <dianzheng> generated.

Analyzing Entity <chw> (Architecture <behavioral>).
Entity <chw> analyzed. Unit <chw> generated.

Analyzing Entity <cnta> (Architecture <behavioral>).
Entity <cnta> analyzed. Unit <cnta> generated.

Analyzing Entity <cont> (Architecture <behavioral>).
Entity <cont> analyzed. Unit <cont> generated.

Analyzing Entity <dz_scan> (Architecture <dz_scan_arch>).
INFO:Xst:1561 - E:/zsx/dianzheng/lie_scan.vhdl line 27: Mux is complete : default of case is discarded
Entity <dz_scan> analyzed. Unit <dz_scan> generated.

Analyzing Entity <hong_lv> (Architecture <hong_lv_arch>).
Entity <hong_lv> analyzed. Unit <hong_lv> generated.

Analyzing Entity <fpq2ms> (Architecture <behavioral>).
Entity <fpq2ms> analyzed. Unit <fpq2ms> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpq2ms>.
    Related source file is E:/zsx/dianzheng/fpq2ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 15-bit comparator lessequal for signal <$n0002>.
    Found 15-bit comparator greatequal for signal <$n0007>.
    Found 15-bit comparator lessequal for signal <$n0008>.
    Found 15-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq2ms> synthesized.


Synthesizing Unit <hong_lv>.
    Related source file is E:/zsx/dianzheng/colour_control.vhdl.
Unit <hong_lv> synthesized.


Synthesizing Unit <dz_scan>.
    Related source file is E:/zsx/dianzheng/lie_scan.vhdl.
    Found 8-bit register for signal <lie>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <dz_scan> synthesized.


Synthesizing Unit <cont>.
    Related source file is E:/zsx/dianzheng/cont.vhdl.
    Found 8-bit 4-to-1 multiplexer for signal <q>.
    Summary:
	inferred   8 Multiplexer(s).
Unit <cont> synthesized.


Synthesizing Unit <cnta>.
    Related source file is E:/zsx/dianzheng/cnta.vhdl.
    Found 3-bit subtractor for signal <q>.
    Found 3-bit up counter for signal <tmp>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 Adder/Subtracter(s).
Unit <cnta> synthesized.


Synthesizing Unit <chw>.
    Related source file is E:/zsx/dianzheng/chw.vhdl.
    Found 32-bit comparator less for signal <$n0002> created at line 24.
    Found 32-bit up counter for signal <cnt>.
    Found 2-bit up counter for signal <tmp>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 Comparator(s).
Unit <chw> synthesized.


Synthesizing Unit <dianzheng>.
    Related source file is E:/zsx/dianzheng/dianzheng.vhf.
Unit <dianzheng> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 3-bit subtractor                  : 1
# Counters                         : 4
 32-bit up counter                 : 1
 15-bit up counter                 : 1
 2-bit up counter                  : 1
 3-bit up counter                  : 1
# Registers                        : 3
 8-bit register                    : 1
 1-bit register                    : 2
# Comparators                      : 4
 32-bit comparator less            : 1
 15-bit comparator lessequal       : 2
 15-bit comparator greatequal      : 1
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Tristates                        : 1
 1-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <dianzheng> ...

Optimizing unit <cont> ...

Optimizing unit <dz_scan> ...

Optimizing unit <fpq2ms> ...

Optimizing unit <chw> ...
Loading device for application Xst from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dianzheng, actual ratio is 10.
FlipFlop XLXI_2_tmp_1 has been replicated 1 time(s)
FlipFlop XLXI_2_tmp_2 has been replicated 1 time(s)
FlipFlop XLXI_2_tmp_0 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      92  out of    768    11%  
 Number of Slice Flip Flops:            65  out of   1536     4%  
 Number of 4 input LUTs:               107  out of   1536     6%  
 Number of bonded IOBs:                 24  out of     96    25%  
 Number of TBUFs:                        1  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 17    |
XLXN_5(XLXI_12_I3_0:O)             | NONE(*)(XLXI_1_cnt_30) | 48    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.315ns (Maximum Frequency: 120.265MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 10.712ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\zsx\dianzheng/_ngo -uc yj3.ucf -p
xc2s50-tq144-6 dianzheng.ngc dianzheng.ngd 

Reading NGO file "E:/zsx/dianzheng/dianzheng.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yj3.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 38000 kilobytes

Writing NGD file "dianzheng.ngd" ...

Writing NGDBUILD log file "dianzheng.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50tq144-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        65 out of  1,536    4%
  Number of 4 input LUTs:            55 out of  1,536    3%
Logic Distribution:
    Number of occupied Slices:                          63 out of    768    8%
    Number of Slices containing only related logic:     63 out of     63  100%
    Number of Slices containing unrelated logic:         0 out of     63    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          107 out of  1,536    6%
      Number used as logic:                        55
      Number used as a route-thru:                 52
   Number of bonded IOBs:            24 out of     92   26%
   Number of Tbufs:                   1 out of    832    1%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  1,213
Additional JTAG gate count for IOBs:  1,200
Peak Memory Usage:  57 MB

NOTES:

   Related log