__projnav.log

8*8点阵的实现

Writing design to file dianzheng.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 404 unrouted;       REAL time: 0 secs 

Phase 2: 393 unrouted;       REAL time: 0 secs 

Phase 3: 61 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   11   |  0.070     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|            XLXN_5          |   Local  |   22   |  1.031     |  3.150      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  60 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file dianzheng.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Thu Mar 29 15:39:39 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module dianzheng . . .
PAR command line: par -w -intstyle ise -ol std -t 1 dianzheng_map.ncd dianzheng.ncd dianzheng.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file
   E:\VHDL\waitpast\dianzheng/lie_scan.vhdl, automatic determination of correct
   order of compilation of files in project file pepExtractor.prj is not
   possible. Please compile your vhdl file(s) individually to find and fix the
   error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl
   file names appear in the project file.
Compiling vhdl file E:\VHDL\waitpast\dianzheng/lie_scan.vhdl in Library work.
ERROR:HDLParsers:164 - E:\VHDL\waitpast\dianzheng/lie_scan.vhdl Line 30. parse
   error, unexpected PROCESS, expecting IF
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/waitpast/dianzheng/lie_scan.vhdl in Library work.
Entity <dz_scan> (Architecture <dz_scan_arch>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/waitpast/dianzheng/colour_control.vhdl in Library
work.
Entity <hong_lv> (Architecture <hong_lv_arch>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/waitpast/dianzheng/fpq2ms.vhdl in Library work.
Entity <fpq2ms> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/VHDL/waitpast/dianzheng/chw.vhdl in Library work.
Architecture behavioral of Entity chw is up to date.
Compiling vhdl file E:/VHDL/waitpast/dianzheng/cnta.vhdl in Library work.
Architecture behavioral of Entity cnta is up to date.
Compiling vhdl file E:/VHDL/waitpast/dianzheng/cont.vhdl in Library work.
Architecture behavioral of Entity cont is up to date.
Compiling vhdl file E:/VHDL/waitpast/dianzheng/lie_scan.vhdl in Library work.
Architecture dz_scan_arch of Entity dz_scan is up to date.
Compiling vhdl file E:/VHDL/waitpast/dianzheng/colour_control.vhdl in Library work.
Architecture hong_lv_arch of Entity hong_lv is up to date.
Compiling vhdl file E:/VHDL/waitpast/dianzheng/fpq2ms.vhdl in Library work.
Architecture behavioral of Entity fpq2ms is up to date.
Compiling vhdl file E:/VHDL/waitpast/dianzheng/dianzheng.vhf in Library work.
Entity <dianzheng> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <dianzheng> (Architecture <behavioral>).
Entity <dianzheng> analyzed. Unit <dianzheng> generated.

Analyzing Entity <chw> (Architecture <behavioral>).
Entity <chw> analyzed. Unit <chw> generated.

Analyzing Entity <cnta> (Architecture <behavioral>).
Entity <cnta> analyzed. Unit <cnta> generated.

Analyzing Entity <cont> (Architecture <behavioral>).
Entity <cont> analyzed. Unit <cont> generated.

Analyzing Entity <dz_scan> (Architecture <dz_scan_arch>).
INFO:Xst:1561 - E:/VHDL/waitpast/dianzheng/lie_scan.vhdl line 27: Mux is complete : default of case is discarded
Entity <dz_scan> analyzed. Unit <dz_scan> generated.

Analyzing Entity <hong_lv> (Architecture <hong_lv_arch>).
Entity <hong_lv> analyzed. Unit <hong_lv> generated.

Analyzing Entity <fpq2ms> (Architecture <behavioral>).
Entity <fpq2ms> analyzed. Unit <fpq2ms> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpq2ms>.
    Related source file is E:/VHDL/waitpast/dianzheng/fpq2ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 15-bit comparator lessequal for signal <$n0002>.
    Found 15-bit comparator greatequal for signal <$n0007>.
    Found 15-bit comparator lessequal for signal <$n0008>.
    Found 15-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq2ms> synthesized.


Synthesizing Unit <hong_lv>.
    Related source file is E:/VHDL/waitpast/dianzheng/colour_control.vhdl.
Unit <hong_lv> synthesized.


Synthesizing Unit <dz_scan>.
    Related source file is E:/VHDL/waitpast/dianzheng/lie_scan.vhdl.
    Found 8-bit register for signal <lie>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <dz_scan> synthesized.


Synthesizing Unit <cont>.
    Related source file is E:/VHDL/waitpast/dianzheng/cont.vhdl.
    Found 8-bit 4-to-1 multiplexer for signal <q>.
    Summary:
	inferred   8 Multiplexer(s).
Unit <cont> synthesized.


Synthesizing Unit <cnta>.
    Related source file is E:/VHDL/waitpast/dianzheng/cnta.vhdl.
    Found 3-bit subtractor for signal <q>.
    Found 3-bit up counter for signal <tmp>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 Adder/Subtracter(s).
Unit <cnta> synthesized.


Synthesizing Unit <chw>.
    Related source file is E:/VHDL/waitpast/dianzheng/chw.vhdl.
    Found 32-bit comparator less for signal <$n0002> created at line 24.
    Found 32-bit up counter for signal <cnt>.
    Found 2-bit up counter for signal <tmp>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 Comparator(s).
Unit <chw> synthesized.


Synthesizing Unit <dianzheng>.
    Related source file is E:/VHDL/waitpast/dianzheng/dianzheng.vhf.
Unit <dianzheng> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 3-bit subtractor                  : 1
# Counters                         : 4
 32-bit up counter                 : 1
 15-bit up counter                 : 1
 2-bit up counter                  : 1
 3-bit up counter                  : 1
# Registers                        : 3
 8-bit register                    : 1
 1-bit register                    : 2
# Comparators                      : 4
 32-bit comparator less            : 1
 15-bit comparator lessequal       : 2
 15-bit comparator greatequal      : 1
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Tristates                        : 1
 1-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <dianzheng> ...

Optimizing unit <cont> ...

Optimizing unit <dz_scan> ...

Optimizing unit <fpq2ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dianzheng, actual ratio is 8.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      77  out of    768    10%  
 Number of Slice Flip Flops:            62  out of   1536     4%  
 Number of 4 input LUTs:               108  out of   1536     7%  
 Number of bonded IOBs:                 24  out of     96    25%  
 Number of TBUFs:                        1  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================