__projnav.log

8*8点阵的实现

Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/DIANZHENG is now defined in a different file: was e:/vhdl/dianzheng/dianzheng.vhf, now is E:/VHDL/waitpast/dianzheng/dianzheng.vhf
WARNING:HDLParsers:3215 - Unit work/DIANZHENG/BEHAVIORAL is now defined in a different file: was e:/vhdl/dianzheng/dianzheng.vhf, now is E:/VHDL/waitpast/dianzheng/dianzheng.vhf
WARNING:HDLParsers:3215 - Unit work/FPQ10MS is now defined in a different file: was e:/vhdl/dianzheng/fpq10ms.vhdl, now is E:/VHDL/waitpast/dianzheng/fpq10ms.vhdl
WARNING:HDLParsers:3215 - Unit work/FPQ10MS/BEHAVIORAL is now defined in a different file: was e:/vhdl/dianzheng/fpq10ms.vhdl, now is E:/VHDL/waitpast/dianzheng/fpq10ms.vhdl
WARNING:HDLParsers:3215 - Unit work/CONT is now defined in a different file: was e:/vhdl/dianzheng/cont.vhdl, now is E:/VHDL/waitpast/dianzheng/cont.vhdl
WARNING:HDLParsers:3215 - Unit work/CONT/BEHAVIORAL is now defined in a different file: was e:/vhdl/dianzheng/cont.vhdl, now is E:/VHDL/waitpast/dianzheng/cont.vhdl
WARNING:HDLParsers:3215 - Unit work/CNTA is now defined in a different file: was e:/vhdl/dianzheng/cnta.vhdl, now is E:/VHDL/waitpast/dianzheng/cnta.vhdl
WARNING:HDLParsers:3215 - Unit work/CNTA/BEHAVIORAL is now defined in a different file: was e:/vhdl/dianzheng/cnta.vhdl, now is E:/VHDL/waitpast/dianzheng/cnta.vhdl
WARNING:HDLParsers:3215 - Unit work/CHW is now defined in a different file: was e:/vhdl/dianzheng/chw.vhdl, now is E:/VHDL/waitpast/dianzheng/chw.vhdl
WARNING:HDLParsers:3215 - Unit work/CHW/BEHAVIORAL is now defined in a different file: was e:/vhdl/dianzheng/chw.vhdl, now is E:/VHDL/waitpast/dianzheng/chw.vhdl
Compiling vhdl file E:/VHDL/waitpast/dianzheng/chw.vhdl in Library work.
Architecture behavioral of Entity chw is up to date.
Compiling vhdl file E:/VHDL/waitpast/dianzheng/cnta.vhdl in Library work.
Architecture behavioral of Entity cnta is up to date.
Compiling vhdl file E:/VHDL/waitpast/dianzheng/cont.vhdl in Library work.
Architecture behavioral of Entity cont is up to date.
Compiling vhdl file E:/VHDL/waitpast/dianzheng/fpq10ms.vhdl in Library work.
Architecture behavioral of Entity fpq10ms is up to date.
Compiling vhdl file E:/VHDL/waitpast/dianzheng/dianzheng.vhf in Library work.
Architecture behavioral of Entity dianzheng is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <dianzheng> (Architecture <behavioral>).
Entity <dianzheng> analyzed. Unit <dianzheng> generated.

Analyzing Entity <chw> (Architecture <behavioral>).
Entity <chw> analyzed. Unit <chw> generated.

Analyzing Entity <cnta> (Architecture <behavioral>).
Entity <cnta> analyzed. Unit <cnta> generated.

Analyzing Entity <cont> (Architecture <behavioral>).
Entity <cont> analyzed. Unit <cont> generated.

Analyzing Entity <fpq10ms> (Architecture <behavioral>).
Entity <fpq10ms> analyzed. Unit <fpq10ms> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpq10ms>.
    Related source file is E:/VHDL/waitpast/dianzheng/fpq10ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 17-bit comparator lessequal for signal <$n0002>.
    Found 17-bit comparator greatequal for signal <$n0007>.
    Found 17-bit comparator lessequal for signal <$n0008>.
    Found 17-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq10ms> synthesized.


Synthesizing Unit <cont>.
    Related source file is E:/VHDL/waitpast/dianzheng/cont.vhdl.
    Found 8-bit 4-to-1 multiplexer for signal <q>.
    Summary:
	inferred   8 Multiplexer(s).
Unit <cont> synthesized.


Synthesizing Unit <cnta>.
    Related source file is E:/VHDL/waitpast/dianzheng/cnta.vhdl.
    Found 3-bit subtractor for signal <q>.
    Found 3-bit up counter for signal <tmp>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 Adder/Subtracter(s).
Unit <cnta> synthesized.


Synthesizing Unit <chw>.
    Related source file is E:/VHDL/waitpast/dianzheng/chw.vhdl.
    Found 32-bit comparator less for signal <$n0002> created at line 24.
    Found 32-bit up counter for signal <cnt>.
    Found 2-bit up counter for signal <tmp>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 Comparator(s).
Unit <chw> synthesized.


Synthesizing Unit <dianzheng>.
    Related source file is E:/VHDL/waitpast/dianzheng/dianzheng.vhf.
Unit <dianzheng> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 3-bit subtractor                  : 1
# Counters                         : 4
 32-bit up counter                 : 1
 17-bit up counter                 : 1
 2-bit up counter                  : 1
 3-bit up counter                  : 1
# Registers                        : 2
 1-bit register                    : 2
# Comparators                      : 4
 32-bit comparator less            : 1
 17-bit comparator lessequal       : 2
 17-bit comparator greatequal      : 1
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Tristates                        : 1
 1-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <dianzheng> ...

Optimizing unit <cont> ...

Optimizing unit <fpq10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dianzheng, actual ratio is 10.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      95  out of    768    12%  
 Number of Slice Flip Flops:            56  out of   1536     3%  
 Number of 4 input LUTs:               138  out of   1536     8%  
 Number of bonded IOBs:                 11  out of     96    11%  
 Number of TBUFs:                        1  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXN_5(XLXI_4_I3_0:O)              | NONE(*)(XLXI_1_cnt_4)  | 37    |
clk                                | BUFGP                  | 19    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.056ns (Maximum Frequency: 110.424MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 10.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\waitpast\dianzheng/_ngo -uc
yj.ucf -p xc2s50-tq144-6 dianzheng.ngc dianzheng.ngd 

Reading NGO file "E:/VHDL/waitpast/dianzheng/dianzheng.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yj.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 54092 kilobytes

Writing NGD file "dianzheng.ngd" ...

Writing NGDBUILD log file "dianzheng.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Map".

Using target part "2s50tq144-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        56 out of  1,536    3%
  Number of 4 input LUTs:            77 out of  1,536    5%
Logic Distribution:
    Number of occupied Slices:                          76 out of    768    9%
    Number of Slices containing only related logic:     76 out of     76  100%
    Number of Slices containing unrelated logic:         0 out of     76    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          135 out of  1,536    8%
      Number used as logic:                        77
      Number used as a route-thru:                 58
   Number of bonded IOBs:            11 out of     92   11%
   Number of Tbufs:                   1 out of    832    1%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  1,393
Additional JTAG gate count for IOBs:  576
Peak Memory Usage:  72 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "dianzheng_map.mrp" for details.
Completed process "Map".

Mapping Module dianzheng . . .
MAP command line:
map -intstyle ise -p xc2s50-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o dianzheng_map.ncd dianzheng.ngd dianzheng.pcf
Mapping Module dianzheng: DONE



Started process "Place & Route".





Constraints file: dianzheng.pcf

Loading device database for application Par from file "dianzheng_map.ncd".
   "dianzheng" is an NCD, version 2.38, device xc2s50, package tq144, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            11 out of 92     11%
      Number of LOCed External IOBs   11 out of 11    100%

   Number of SLICEs                   76 out of 768     9%

   Number of GCLKs                     1 out of 4      25%
   Number of TBUFs                     1 out of 832     1%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989858) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
...
Phase 5.8 (Checksum:996c12) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs