__projnav.log

8*8点阵的实现

TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXN_5(XLXI_4_I3_0:O)              | NONE(*)(XLXI_2_tmp_1)  | 37    |
clk                                | BUFGP                  | 19    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.056ns (Maximum Frequency: 110.424MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 10.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\dianzheng/_ngo -uc yj.ucf -p
xc2s50-tq144-6 dianzheng.ngc dianzheng.ngd 

Reading NGO file "e:/vhdl/dianzheng/dianzheng.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yj.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 40164 kilobytes

Writing NGD file "dianzheng.ngd" ...

Writing NGDBUILD log file "dianzheng.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\dianzheng/_ngo -uc yj.ucf -p
xc2s50-tq144-6 dianzheng.ngc dianzheng.ngd 

Reading NGO file "e:/vhdl/dianzheng/dianzheng.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yj.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 41188 kilobytes

Writing NGD file "dianzheng.ngd" ...

Writing NGDBUILD log file "dianzheng.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50tq144-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB
   component:
   	PAD symbol "q<2>" (Pad Signal = q<2>)
   	BUF symbol "q_2_OBUF" (Output Signal = q<2>)
   Each of the following constraints specifies an illegal physical site for a
   component of type IOB:
   	Symbol "q<2>" (LOC=P91)
   Please correct the constraints accordingly.

Mapping completed.
See MAP report file "dianzheng_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   1
Number of warnings :   0
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module dianzheng . . .
MAP command line:
map -intstyle ise -p xc2s50-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o dianzheng_map.ncd dianzheng.ngd dianzheng.pcf
Mapping Module dianzheng: failed


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\dianzheng/_ngo -uc yj.ucf -p
xc2s50-tq144-6 dianzheng.ngc dianzheng.ngd 

Reading NGO file "e:/vhdl/dianzheng/dianzheng.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yj.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 41188 kilobytes

Writing NGD file "dianzheng.ngd" ...

Writing NGDBUILD log file "dianzheng.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50tq144-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        56 out of  1,536    3%
  Number of 4 input LUTs:            77 out of  1,536    5%
Logic Distribution:
    Number of occupied Slices:                          76 out of    768    9%
    Number of Slices containing only related logic:     76 out of     76  100%
    Number of Slices containing unrelated logic:         0 out of     76    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          135 out of  1,536    8%
      Number used as logic:                        77
      Number used as a route-thru:                 58
   Number of bonded IOBs:            11 out of     92   11%
   Number of Tbufs:                   1 out of    832    1%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  1,393
Additional JTAG gate count for IOBs:  576
Peak Memory Usage:  59 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "dianzheng_map.mrp" for details.
Completed process "Map".

Mapping Module dianzheng . . .
MAP command line:
map -intstyle ise -p xc2s50-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o dianzheng_map.ncd dianzheng.ngd dianzheng.pcf
Mapping Module dianzheng: DONE



Started process "Place & Route".





Constraints file: dianzheng.pcf
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 55
   days, this program will not operate. For more information about thisproduct,
   please refer to the Evaluation Agreement, which was shipped toyou along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact yourlocal
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to:[e-mail]
   Thank You!

Loading device database for application Par from file "dianzheng_map.ncd".
   "dianzheng" is an NCD, version 2.38, device xc2s50, package tq144, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            11 out of 92     11%
      Number of LOCed External IOBs   11 out of 11    100%

   Number of SLICEs                   76 out of 768     9%

   Number of GCLKs                     1 out of 4      25%
   Number of TBUFs                     1 out of 832     1%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989858) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
...
Phase 5.8 (Checksum:996c12) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file dianzheng.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 404 unrouted;       REAL time: 0 secs 

Phase 2: 393 unrouted;       REAL time: 0 secs 

Phase 3: 61 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   11   |  0.070     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|            XLXN_5          |   Local  |   22   |  1.031     |  3.150      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  49 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file dianzheng.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Mon Mar 19 17:27:48 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module dianzheng . . .
PAR command line: par -w -intstyle ise -ol std -t 1 dianzheng_map.ncd dianzheng.ncd dianzheng.pcf
PAR completed successfully