dianzheng.syr

8*8点阵的实现

 2-bit up counter                  : 1
 3-bit up counter                  : 1
# Registers                        : 3
 8-bit register                    : 1
 1-bit register                    : 2
# Comparators                      : 4
 32-bit comparator less            : 1
 15-bit comparator lessequal       : 2
 15-bit comparator greatequal      : 1
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Tristates                        : 1
 1-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <dianzheng> ...

Optimizing unit <cont> ...

Optimizing unit <dz_scan> ...

Optimizing unit <fpq2ms> ...

Optimizing unit <chw> ...
Loading device for application Xst from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dianzheng, actual ratio is 9.
FlipFlop XLXI_2_tmp_1 has been replicated 1 time(s)
FlipFlop XLXI_2_tmp_0 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : dianzheng.ngr
Top Level Output File Name         : dianzheng
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 25

Macro Statistics :
# Registers                        : 7
#      1-bit register              : 2
#      32-bit register             : 4
#      8-bit register              : 1
# Multiplexers                     : 1
#      8-bit 4-to-1 multiplexer    : 1
# Tristates                        : 1
#      1-bit tristate buffer       : 1
# Adders/Subtractors               : 4
#      32-bit adder                : 4
# Comparators                      : 4
#      15-bit comparator greatequal: 1
#      15-bit comparator lessequal : 2
#      32-bit comparator less      : 1

Cell Usage :
# BELS                             : 226
#      GND                         : 1
#      LUT1                        : 49
#      LUT1_L                      : 9
#      LUT2                        : 10
#      LUT2_L                      : 2
#      LUT3                        : 4
#      LUT3_D                      : 1
#      LUT3_L                      : 3
#      LUT4                        : 20
#      LUT4_L                      : 8
#      MUXCY                       : 66
#      MUXF5                       : 7
#      VCC                         : 1
#      XORCY                       : 45
# FlipFlops/Latches                : 64
#      FD                          : 3
#      FDE                         : 2
#      FDR                         : 57
#      FDRS                        : 1
#      FDS                         : 1
# Tri-States                       : 1
#      BUFT                        : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 24
#      OBUF                        : 24
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      88  out of    768    11%  
 Number of Slice Flip Flops:            64  out of   1536     4%  
 Number of 4 input LUTs:               106  out of   1536     6%  
 Number of bonded IOBs:                 24  out of     96    25%  
 Number of TBUFs:                        1  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 17    |
XLXN_5(XLXI_12_I3_0:O)             | NONE(*)(XLXI_1_cnt_6)  | 47    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.273ns (Maximum Frequency: 120.875MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 11.531ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               7.948ns (Levels of Logic = 2)
  Source:            XLXI_12_a_5 (FF)
  Destination:       XLXI_12_a_14 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_12_a_5 to XLXI_12_a_14
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              5   1.085   1.566  XLXI_12_a_5 (XLXI_12_a_5)
     LUT4:I0->O            1   0.549   1.035  XLXI_12__n000134 (CHOICE77)
     LUT4:I0->O           15   0.549   2.430  XLXI_12__n000145 (XLXI_12__n0001)
     FDR:R                     0.734          XLXI_12_a_0
    ----------------------------------------
    Total                      7.948ns (2.917ns logic, 5.031ns route)
                                       (36.7% logic, 63.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_12_I3_0:O'
Delay:               8.273ns (Levels of Logic = 11)
  Source:            XLXI_1_cnt_4 (FF)
  Destination:       XLXI_1_tmp_1 (FF)
  Source Clock:      XLXI_12_I3_0:O rising
  Destination Clock: XLXI_12_I3_0:O rising

  Data Path: XLXI_1_cnt_4 to XLXI_1_tmp_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.085   1.206  XLXI_1_cnt_4 (XLXI_1_cnt_4)
     LUT1_L:I0->LO         1   0.549   0.000  XLXI_1_cnt<4>_rt (XLXI_1_cnt<4>_rt)
     MUXCY:S->O            1   0.659   0.000  XLXI_1_Andcy (XLXI_1_And_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_1_norcy (XLXI_1_nor_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_1_Andcy_rn_0 (XLXI_1_And_cyo1)
     MUXCY:CI->O           1   0.042   0.000  XLXI_1_Andcy_rn_1 (XLXI_1_And_cyo2)
     MUXCY:CI->O           1   0.042   0.000  XLXI_1_norcy_rn_0 (XLXI_1_nor_cyo1)
     MUXCY:CI->O           1   0.042   0.000  XLXI_1_norcy_rn_1 (XLXI_1_nor_cyo2)
     MUXCY:CI->O           1   0.042   0.000  XLXI_1_norcy_rn_2 (XLXI_1_nor_cyo3)
     MUXCY:CI->O           1   0.042   0.000  XLXI_1_norcy_rn_3 (XLXI_1_nor_cyo4)
     MUXCY:CI->O           1   0.042   0.000  XLXI_1_norcy_rn_4 (XLXI_1_nor_cyo5)
     MUXCY:CI->O          34   0.042   3.510  XLXI_1_GE_stagecy (XLXI_1_GE_stage_cyo)
     FDE:CE                    0.886          XLXI_1_tmp_0
    ----------------------------------------
    Total                      8.273ns (3.557ns logic, 4.716ns route)
                                       (43.0% logic, 57.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_12_I3_0:O'
Offset:              11.531ns (Levels of Logic = 3)
  Source:            XLXI_1_tmp_0 (FF)
  Destination:       y<5> (PAD)
  Source Clock:      XLXI_12_I3_0:O rising

  Data Path: XLXI_1_tmp_0 to y<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q             17   1.085   2.610  XLXI_1_tmp_0 (XLXI_1_tmp_0)
     LUT2:I1->O            1   0.549   1.035  XLXI_3_Mmux_q_inst_mux_f5_5_SW0 (N3605)
     LUT4:I3->O            1   0.549   1.035  XLXI_3_Mmux_q_inst_mux_f5_5 (y_5_OBUF)
     OBUF:I->O                 4.668          y_5_OBUF (y<5>)
    ----------------------------------------
    Total                     11.531ns (6.851ns logic, 4.680ns route)
                                       (59.4% logic, 40.6% route)

=========================================================================
CPU : 3.78 / 5.23 s | Elapsed : 4.00 / 5.00 s
 
--> 

Total memory usage is 56536 kilobytes