ps2_lcd1602_1.syr

与PS2的通信

---------------
Speed Grade: -5

   Minimum period: 7.809ns (Maximum Frequency: 128.064MHz)
   Minimum input arrival time before clock: 3.506ns
   Maximum output required time after clock: 6.280ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 4.991ns (frequency: 200.345MHz)
  Total number of paths / destination ports: 454 / 78
-------------------------------------------------------------------------
Delay:               4.991ns (Levels of Logic = 7)
  Source:            a1/n1_0 (FF)
  Destination:       a1/n1_0 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: a1/n1_0 to a1/n1_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.626   1.040  a1/n1_0 (a1/n1_0)
     LUT4:I0->O            1   0.479   0.000  a1/Mcompar__n0031_andlut (a1/N47)
     MUXCY:S->O            1   0.435   0.000  a1/Mcompar__n0031_andcy (a1/Mcompar__n0031_and_cyo)
     MUXCY:CI->O           1   0.056   0.000  a1/Mcompar__n0031_andcy_rn_0 (a1/Mcompar__n0031_and_cyo1)
     MUXCY:CI->O           1   0.056   0.000  a1/Mcompar__n0031_norcy (a1/Mcompar__n0031_nor_cyo)
     MUXCY:CI->O           1   0.056   0.000  a1/Mcompar__n0031_andcy_rn_1 (a1/Mcompar__n0031_and_cyo2)
     MUXCY:CI->O           1   0.056   0.000  a1/Mcompar__n0031_norcy_rn_0 (a1/Mcompar__n0031_nor_cyo1)
     MUXCY:CI->O          16   0.246   1.051  a1/Mcompar__n0031_andcy_rn_2 (a1/Mcompar__n0031_and_cyo3)
     FDR:R                     0.892          a1/n1_0
    ----------------------------------------
    Total                      4.991ns (2.900ns logic, 2.092ns route)
                                       (58.1% logic, 41.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'a1/Clk_Out1'
  Clock period: 7.809ns (frequency: 128.064MHz)
  Total number of paths / destination ports: 899 / 29
-------------------------------------------------------------------------
Delay:               7.809ns (Levels of Logic = 12)
  Source:            a1/cnt1_2_1 (FF)
  Destination:       a1/LCD_Data_7 (FF)
  Source Clock:      a1/Clk_Out1 rising
  Destination Clock: a1/Clk_Out1 rising

  Data Path: a1/cnt1_2_1 to a1/LCD_Data_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              3   0.626   1.066  a1/cnt1_2_1 (a1/cnt1_2_1)
     LUT2_D:I0->O          2   0.479   0.768  a1/_n0023<1>1_SW0 (N1045)
     LUT4:I3->O            1   0.479   0.704  a1/LCD1602__n0027<1>lut_SW0 (N1094)
     LUT4_L:I3->LO         1   0.479   0.000  a1/LCD1602__n0027<1>lut (a1/N42)
     MUXCY:S->O            1   0.435   0.000  a1/LCD1602__n0027<1>cy (a1/LCD1602__n0027<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  a1/LCD1602__n0027<2>cy (a1/LCD1602__n0027<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  a1/LCD1602__n0027<3>cy (a1/LCD1602__n0027<3>_cyo)
     MUXCY:CI->O           1   0.056   0.000  a1/LCD1602__n0027<4>cy (a1/LCD1602__n0027<4>_cyo)
     MUXCY:CI->O           2   0.056   0.000  a1/LCD1602__n0027<5>cy (a1/LCD1602__n0027<5>_cyo)
     MUXCY:CI->O           0   0.056   0.000  a1/LCD1602__n0027<6>cy (a1/LCD1602__n0027<6>_cyo)
     XORCY:CI->O           1   0.786   0.740  a1/LCD1602__n0027<7>_xor (a1/_n0027<7>)
     LUT3_L:I2->LO         1   0.479   0.000  a1/_n0018<7>1111_G (N1158)
     MUXF5:I1->O           1   0.314   0.000  a1/_n0018<7>1111 (a1/_n0018<7>)
     FDE:D                     0.176          a1/LCD_Data_7
    ----------------------------------------
    Total                      7.809ns (4.531ns logic, 3.278ns route)
                                       (58.0% logic, 42.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'a0/hit_11'
  Clock period: 5.539ns (frequency: 180.545MHz)
  Total number of paths / destination ports: 160 / 90
-------------------------------------------------------------------------
Delay:               5.539ns (Levels of Logic = 2)
  Source:            a1/key_cnt_1 (FF)
  Destination:       a1/inst_Mram_mem81 (RAM)
  Source Clock:      a0/hit_11 rising
  Destination Clock: a0/hit_11 rising

  Data Path: a1/key_cnt_1 to a1/inst_Mram_mem81
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             53   0.626   1.972  a1/key_cnt_1 (a1/key_cnt_1)
     LUT4_D:I0->O          1   0.479   0.740  a1/_n00071 (a1/N53)
     LUT3:I2->O            8   0.479   0.921  a1/write_ctrl1 (a1/N6)
     RAM16X1D:WE               0.322          a1/inst_Mram_mem81
    ----------------------------------------
    Total                      5.539ns (1.906ns logic, 3.633ns route)
                                       (34.4% logic, 65.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'a0/N3'
  Clock period: 6.052ns (frequency: 165.244MHz)
  Total number of paths / destination ports: 71 / 11
-------------------------------------------------------------------------
Delay:               6.052ns (Levels of Logic = 5)
  Source:            a0/hit_cnt_2 (LATCH)
  Destination:       a0/hit_cnt_10 (LATCH)
  Source Clock:      a0/N3 falling
  Destination Clock: a0/N3 falling

  Data Path: a0/hit_cnt_2 to a0/hit_cnt_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               5   0.551   1.078  a0/hit_cnt_2 (a0/hit_cnt_2)
     LUT2:I0->O            1   0.479   0.704  a0/Ker01_SW0 (N943)
     LUT4_D:I3->LO         1   0.479   0.159  a0/Ker01 (N1174)
     LUT3:I2->O            3   0.479   0.830  a0/Ker111 (a0/N11)
     LUT3_D:I2->LO         1   0.479   0.159  a0/Ker81 (N1173)
     LUT3_L:I2->LO         1   0.479   0.000  a0/_n0014<10>1 (a0/_n0014<10>)
     LD:D                      0.176          a0/hit_cnt_10
    ----------------------------------------
    Total                      6.052ns (3.122ns logic, 2.930ns route)
                                       (51.6% logic, 48.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'a1/Clk_Out1'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              2.194ns (Levels of Logic = 1)
  Source:            Reset2 (PAD)
  Destination:       a1/LCD_Data_0 (FF)
  Destination Clock: a1/Clk_Out1 rising

  Data Path: Reset2 to a1/LCD_Data_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.715   0.955  Reset2_IBUF (Reset2_IBUF)
     FDE:CE                    0.524          a1/LCD_Data_6
    ----------------------------------------
    Total                      2.194ns (1.239ns logic, 0.955ns route)
                                       (56.5% logic, 43.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 6 / 6
-------------------------------------------------------------------------
Offset:              3.506ns (Levels of Logic = 3)
  Source:            ps2_dta (PAD)
  Destination:       a0/parset (FF)
  Destination Clock: CLK rising

  Data Path: ps2_dta to a0/parset
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.715   0.806  ps2_dta_IBUF (ps2_dta_IBUF)
     LUT4:I3->O            1   0.479   0.851  a0/n_parset1 (a0/N5)
     LUT2:I1->O            1   0.479   0.000  a0/n_parset2 (a0/n_parset)
     FDP:D                     0.176          a0/parset
    ----------------------------------------
    Total                      3.506ns (1.849ns logic, 1.657ns route)
                                       (52.7% logic, 47.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.280ns (Levels of Logic = 1)
  Source:            a1/Clk_Out (FF)
  Destination:       LCD_EN (PAD)
  Source Clock:      CLK rising

  Data Path: a1/Clk_Out to LCD_EN
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.626   0.745  a1/Clk_Out (a1/Clk_Out1)
     OBUF:I->O                 4.909          LCD_EN_OBUF (LCD_EN)
    ----------------------------------------
    Total                      6.280ns (5.535ns logic, 0.745ns route)
                                       (88.1% logic, 11.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'a1/Clk_Out1'
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Offset:              6.216ns (Levels of Logic = 1)
  Source:            a1/LCD_RS (FF)
  Destination:       LCD_RS (PAD)
  Source Clock:      a1/Clk_Out1 rising

  Data Path: a1/LCD_RS to LCD_RS
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.626   0.681  a1/LCD_RS (a1/LCD_RS)
     OBUF:I->O                 4.909          LCD_RS_OBUF (LCD_RS)
    ----------------------------------------
    Total                      6.216ns (5.535ns logic, 0.681ns route)
                                       (89.0% logic, 11.0% route)

=========================================================================
CPU : 18.25 / 19.00 s | Elapsed : 18.00 / 19.00 s
 
--> 

Total memory usage is 115348 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    6 (   0 filtered)
Number of infos    :    3 (   0 filtered)