seg70.tan.rpt

7 段数码管实验（包括两个实验） ７段数码管测试实验１：以动态扫描方式在８位数码管“同时”显示０—7

+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------+
; tco                                                                        ;
+-------+--------------+------------+--------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To         ; From Clock ;
+-------+--------------+------------+--------------+------------+------------+
; N/A   ; None         ; 14.484 ns  ; cnt_scan[15] ; en[2]      ; clk        ;
; N/A   ; None         ; 14.445 ns  ; cnt_scan[15] ; dataout[7] ; clk        ;
; N/A   ; None         ; 14.442 ns  ; cnt_scan[15] ; dataout[5] ; clk        ;
; N/A   ; None         ; 14.374 ns  ; cnt_scan[14] ; dataout[7] ; clk        ;
; N/A   ; None         ; 14.337 ns  ; cnt_scan[14] ; en[2]      ; clk        ;
; N/A   ; None         ; 14.295 ns  ; cnt_scan[14] ; dataout[5] ; clk        ;
; N/A   ; None         ; 14.269 ns  ; cnt_scan[13] ; dataout[7] ; clk        ;
; N/A   ; None         ; 14.004 ns  ; cnt_scan[15] ; dataout[6] ; clk        ;
; N/A   ; None         ; 13.975 ns  ; cnt_scan[13] ; en[2]      ; clk        ;
; N/A   ; None         ; 13.950 ns  ; cnt_scan[13] ; dataout[2] ; clk        ;
; N/A   ; None         ; 13.933 ns  ; cnt_scan[13] ; dataout[5] ; clk        ;
; N/A   ; None         ; 13.884 ns  ; cnt_scan[15] ; dataout[4] ; clk        ;
; N/A   ; None         ; 13.858 ns  ; cnt_scan[14] ; dataout[6] ; clk        ;
; N/A   ; None         ; 13.790 ns  ; cnt_scan[14] ; dataout[2] ; clk        ;
; N/A   ; None         ; 13.734 ns  ; cnt_scan[14] ; dataout[4] ; clk        ;
; N/A   ; None         ; 13.538 ns  ; cnt_scan[13] ; en[0]      ; clk        ;
; N/A   ; None         ; 13.532 ns  ; cnt_scan[13] ; en[1]      ; clk        ;
; N/A   ; None         ; 13.531 ns  ; cnt_scan[13] ; en[7]      ; clk        ;
; N/A   ; None         ; 13.495 ns  ; cnt_scan[13] ; dataout[6] ; clk        ;
; N/A   ; None         ; 13.480 ns  ; cnt_scan[14] ; en[5]      ; clk        ;
; N/A   ; None         ; 13.472 ns  ; cnt_scan[14] ; en[3]      ; clk        ;
; N/A   ; None         ; 13.422 ns  ; cnt_scan[15] ; dataout[1] ; clk        ;
; N/A   ; None         ; 13.419 ns  ; cnt_scan[15] ; dataout[2] ; clk        ;
; N/A   ; None         ; 13.369 ns  ; cnt_scan[13] ; dataout[4] ; clk        ;
; N/A   ; None         ; 13.352 ns  ; cnt_scan[14] ; dataout[1] ; clk        ;
; N/A   ; None         ; 13.319 ns  ; cnt_scan[13] ; en[5]      ; clk        ;
; N/A   ; None         ; 13.314 ns  ; cnt_scan[15] ; en[6]      ; clk        ;
; N/A   ; None         ; 13.312 ns  ; cnt_scan[13] ; en[3]      ; clk        ;
; N/A   ; None         ; 13.284 ns  ; cnt_scan[13] ; en[6]      ; clk        ;
; N/A   ; None         ; 13.246 ns  ; cnt_scan[13] ; dataout[1] ; clk        ;
; N/A   ; None         ; 13.216 ns  ; cnt_scan[15] ; en[0]      ; clk        ;
; N/A   ; None         ; 13.210 ns  ; cnt_scan[15] ; en[1]      ; clk        ;
; N/A   ; None         ; 13.208 ns  ; cnt_scan[15] ; en[7]      ; clk        ;
; N/A   ; None         ; 13.004 ns  ; cnt_scan[13] ; dataout[3] ; clk        ;
; N/A   ; None         ; 12.907 ns  ; cnt_scan[14] ; en[6]      ; clk        ;
; N/A   ; None         ; 12.843 ns  ; cnt_scan[14] ; en[0]      ; clk        ;
; N/A   ; None         ; 12.837 ns  ; cnt_scan[14] ; en[1]      ; clk        ;
; N/A   ; None         ; 12.835 ns  ; cnt_scan[14] ; en[7]      ; clk        ;
; N/A   ; None         ; 12.815 ns  ; cnt_scan[15] ; en[5]      ; clk        ;
; N/A   ; None         ; 12.807 ns  ; cnt_scan[15] ; en[3]      ; clk        ;
; N/A   ; None         ; 12.724 ns  ; cnt_scan[13] ; en[4]      ; clk        ;
; N/A   ; None         ; 12.667 ns  ; cnt_scan[14] ; dataout[3] ; clk        ;
; N/A   ; None         ; 12.564 ns  ; cnt_scan[14] ; en[4]      ; clk        ;
; N/A   ; None         ; 12.273 ns  ; cnt_scan[15] ; dataout[3] ; clk        ;
; N/A   ; None         ; 12.192 ns  ; cnt_scan[15] ; en[4]      ; clk        ;
+-------+--------------+------------+--------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Apr 28 17:20:30 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seg70 -c seg70
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 201.09 MHz between source register "cnt_scan[3]" and destination register "cnt_scan[12]" (period= 4.973 ns)
    Info: + Longest register to register delay is 4.264 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y10_N5; Fanout = 3; REG Node = 'cnt_scan[3]'
        Info: 2: + IC(0.892 ns) + CELL(0.978 ns) = 1.870 ns; Loc. = LC_X10_Y10_N5; Fanout = 2; COMB Node = 'cnt_scan[3]~82'
        Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 1.993 ns; Loc. = LC_X10_Y10_N6; Fanout = 2; COMB Node = 'cnt_scan[4]~81'
        Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.116 ns; Loc. = LC_X10_Y10_N7; Fanout = 2; COMB Node = 'cnt_scan[5]~80'
        Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.239 ns; Loc. = LC_X10_Y10_N8; Fanout = 2; COMB Node = 'cnt_scan[6]~79'
        Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 2.638 ns; Loc. = LC_X10_Y10_N9; Fanout = 6; COMB Node = 'cnt_scan[7]~78'
        Info: 7: + IC(0.000 ns) + CELL(1.626 ns) = 4.264 ns; Loc. = LC_X11_Y10_N4; Fanout = 2; REG Node = 'cnt_scan[12]'
        Info: Total cell delay = 3.372 ns ( 79.08 % )
        Info: Total interconnect delay = 0.892 ns ( 20.92 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 7.323 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(5.273 ns) + CELL(0.918 ns) = 7.323 ns; Loc. = LC_X11_Y10_N4; Fanout = 2; REG Node = 'cnt_scan[12]'
            Info: Total cell delay = 2.050 ns ( 27.99 % )
            Info: Total interconnect delay = 5.273 ns ( 72.01 % )
        Info: - Longest clock path from clock "clk" to source register is 7.323 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(5.273 ns) + CELL(0.918 ns) = 7.323 ns; Loc. = LC_X10_Y10_N5; Fanout = 3; REG Node = 'cnt_scan[3]'
            Info: Total cell delay = 2.050 ns ( 27.99 % )
            Info: Total interconnect delay = 5.273 ns ( 72.01 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "en[2]" through register "cnt_scan[15]" is 14.484 ns
    Info: + Longest clock path from clock "clk" to source register is 7.323 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(5.273 ns) + CELL(0.918 ns) = 7.323 ns; Loc. = LC_X11_Y10_N7; Fanout = 15; REG Node = 'cnt_scan[15]'
        Info: Total cell delay = 2.050 ns ( 27.99 % )
        Info: Total interconnect delay = 5.273 ns ( 72.01 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 6.785 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y10_N7; Fanout = 15; REG Node = 'cnt_scan[15]'
        Info: 2: + IC(1.413 ns) + CELL(0.740 ns) = 2.153 ns; Loc. = LC_X12_Y10_N3; Fanout = 2; COMB Node = 'Mux7~94'
        Info: 3: + IC(2.310 ns) + CELL(2.322 ns) = 6.785 ns; Loc. = PIN_124; Fanout = 0; PIN Node = 'en[2]'
        Info: Total cell delay = 3.062 ns ( 45.13 % )
        Info: Total interconnect delay = 3.723 ns ( 54.87 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Apr 28 17:20:31 2007
    Info: Elapsed time: 00:00:01