seg70.fit.rpt

7 段数码管实验（包括两个实验） ７段数码管测试实验１：以动态扫描方式在８位数码管“同时”显示０—7

; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                    ;
+--------------------------------------------------------------------------------+---------+
; Name                                                                           ; Value   ;
+--------------------------------------------------------------------------------+---------+
; Mid Wire Use - Fit Attempt 1                                                   ; 1       ;
; Mid Slack - Fit Attempt 1                                                      ; -9625   ;
; Internal Atom Count - Fit Attempt 1                                            ; 30      ;
; LE/ALM Count - Fit Attempt 1                                                   ; 30      ;
; LAB Count - Fit Attempt 1                                                      ; 4       ;
; Outputs per Lab - Fit Attempt 1                                                ; 4.250   ;
; Inputs per LAB - Fit Attempt 1                                                 ; 1.500   ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 1.000   ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:4     ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:4     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:4     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:4     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:2;1:2 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:2;1:2 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:4     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:4     ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:4     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:2;2:2 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:2;1:2 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:4     ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:2;1:2 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:4     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:2;1:2 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:2;1:2 ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:4     ;
; LEs in Chains - Fit Attempt 1                                                  ; 15      ;
; LEs in Long Chains - Fit Attempt 1                                             ; 15      ;
; LABs with Chains - Fit Attempt 1                                               ; 2       ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0       ;
; Time - Fit Attempt 1                                                           ; 0       ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.016   ;
+--------------------------------------------------------------------------------+---------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Wire Use - Fit Attempt 1      ; 0      ;
; Early Slack - Fit Attempt 1         ; -15354 ;
; Mid Wire Use - Fit Attempt 1        ; 1      ;
; Mid Slack - Fit Attempt 1           ; -13583 ;
; Late Wire Use - Fit Attempt 1       ; 1      ;
; Late Slack - Fit Attempt 1          ; -13576 ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.204  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -13762 ;
; Early Wire Use - Fit Attempt 1      ; 0      ;
; Peak Regional Wire - Fit Attempt 1  ; 1      ;
; Mid Slack - Fit Attempt 1           ; -13973 ;
; Late Slack - Fit Attempt 1          ; -13973 ;
; Late Slack - Fit Attempt 1          ; -13973 ;
; Late Wire Use - Fit Attempt 1       ; 1      ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.031  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Apr 28 17:20:21 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off seg70 -c seg70
Info: Selected device EPM1270T144C5 for design "seg70"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM1270T144I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock
Info: Pin "clk" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted signal "rst" to use Global clock
Info: Pin "rst" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 6.499 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y10; Fanout = 17; REG Node = 'cnt_scan[13]'
    Info: 2: + IC(1.584 ns) + CELL(0.200 ns) = 1.784 ns; Loc. = LAB_X12_Y10; Fanout = 2; COMB Node = 'Mux7~94'
    Info: 3: + IC(2.393 ns) + CELL(2.322 ns) = 6.499 ns; Loc. = PIN_111; Fanout = 0; PIN Node = 'dataout[5]'
    Info: Total cell delay = 2.522 ns ( 38.81 % )
    Info: Total interconnect delay = 3.977 ns ( 61.19 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location x9_y0 to location x17_y11
Info: Fitter routing operations ending: elapsed time is 00:00:00
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin dataout[0] has VCC driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Apr 28 17:20:26 2007
    Info: Elapsed time: 00:00:05


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/7段数码管/seg70/seg70.fit.smsg.