seg73.tan.qmsg

7 段数码管实验（包括两个实验） ７段数码管测试实验１：以动态扫描方式在８位数码管“同时”显示０—7

{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[7\] cntlast\[2\] 30.803 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[7\]\" through register \"cntlast\[2\]\" is 30.803 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 22.133 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 22.133 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 29 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 29; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "" { clk } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(1.294 ns) 7.096 ns div_cnt\[24\] 2 REG LC_X11_Y4_N7 6 " "Info: 2: + IC(4.670 ns) + CELL(1.294 ns) = 7.096 ns; Loc. = LC_X11_Y4_N7; Fanout = 6; REG Node = 'div_cnt\[24\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "5.964 ns" { clk div_cnt[24] } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.203 ns) + CELL(1.294 ns) 11.593 ns first_over 3 REG LC_X12_Y7_N3 5 " "Info: 3: + IC(3.203 ns) + CELL(1.294 ns) = 11.593 ns; Loc. = LC_X12_Y7_N3; Fanout = 5; REG Node = 'first_over'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "4.497 ns" { div_cnt[24] first_over } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.291 ns) + CELL(1.294 ns) 16.178 ns second_over 4 REG LC_X12_Y3_N2 5 " "Info: 4: + IC(3.291 ns) + CELL(1.294 ns) = 16.178 ns; Loc. = LC_X12_Y3_N2; Fanout = 5; REG Node = 'second_over'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "4.585 ns" { first_over second_over } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.427 ns) + CELL(1.294 ns) 19.899 ns third_over 5 REG LC_X13_Y10_N9 5 " "Info: 5: + IC(2.427 ns) + CELL(1.294 ns) = 19.899 ns; Loc. = LC_X13_Y10_N9; Fanout = 5; REG Node = 'third_over'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "3.721 ns" { second_over third_over } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.316 ns) + CELL(0.918 ns) 22.133 ns cntlast\[2\] 6 REG LC_X12_Y10_N0 5 " "Info: 6: + IC(1.316 ns) + CELL(0.918 ns) = 22.133 ns; Loc. = LC_X12_Y10_N0; Fanout = 5; REG Node = 'cntlast\[2\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "2.234 ns" { third_over cntlast[2] } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.226 ns 32.65 % " "Info: Total cell delay = 7.226 ns ( 32.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.907 ns 67.35 % " "Info: Total interconnect delay = 14.907 ns ( 67.35 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "22.133 ns" { clk div_cnt[24] first_over second_over third_over cntlast[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "22.133 ns" { clk clk~combout div_cnt[24] first_over second_over third_over cntlast[2] } { 0.000ns 0.000ns 4.670ns 3.203ns 3.291ns 2.427ns 1.316ns } { 0.000ns 1.132ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.294 ns + Longest register pin " "Info: + Longest register to pin delay is 8.294 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cntlast\[2\] 1 REG LC_X12_Y10_N0 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y10_N0; Fanout = 5; REG Node = 'cntlast\[2\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "" { cntlast[2] } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.968 ns) + CELL(0.511 ns) 1.479 ns data4\[2\]~349 2 COMB LC_X12_Y10_N9 7 " "Info: 2: + IC(0.968 ns) + CELL(0.511 ns) = 1.479 ns; Loc. = LC_X12_Y10_N9; Fanout = 7; COMB Node = 'data4\[2\]~349'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "1.479 ns" { cntlast[2] data4[2]~349 } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.914 ns) 3.619 ns Mux~194 3 COMB LC_X13_Y10_N7 1 " "Info: 3: + IC(1.226 ns) + CELL(0.914 ns) = 3.619 ns; Loc. = LC_X13_Y10_N7; Fanout = 1; COMB Node = 'Mux~194'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "2.140 ns" { data4[2]~349 Mux~194 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.353 ns) + CELL(2.322 ns) 8.294 ns dataout\[7\] 4 PIN PIN_109 0 " "Info: 4: + IC(2.353 ns) + CELL(2.322 ns) = 8.294 ns; Loc. = PIN_109; Fanout = 0; PIN Node = 'dataout\[7\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "4.675 ns" { Mux~194 dataout[7] } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.747 ns 45.18 % " "Info: Total cell delay = 3.747 ns ( 45.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.547 ns 54.82 % " "Info: Total interconnect delay = 4.547 ns ( 54.82 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "8.294 ns" { cntlast[2] data4[2]~349 Mux~194 dataout[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.294 ns" { cntlast[2] data4[2]~349 Mux~194 dataout[7] } { 0.000ns 0.968ns 1.226ns 2.353ns } { 0.000ns 0.511ns 0.914ns 2.322ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "22.133 ns" { clk div_cnt[24] first_over second_over third_over cntlast[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "22.133 ns" { clk clk~combout div_cnt[24] first_over second_over third_over cntlast[2] } { 0.000ns 0.000ns 4.670ns 3.203ns 3.291ns 2.427ns 1.316ns } { 0.000ns 1.132ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "8.294 ns" { cntlast[2] data4[2]~349 Mux~194 dataout[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.294 ns" { cntlast[2] data4[2]~349 Mux~194 dataout[7] } { 0.000ns 0.968ns 1.226ns 2.353ns } { 0.000ns 0.511ns 0.914ns 2.322ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 12:14:18 2006 " "Info: Processing ended: Sat Feb 18 12:14:18 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}