seg73.tan.qmsg

7 段数码管实验（包括两个实验） ７段数码管测试实验１：以动态扫描方式在８位数码管“同时”显示０—7

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "first_over " "Info: Detected ripple clock \"first_over\" as buffer" {  } { { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 26 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "first_over" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "div_cnt\[24\] " "Info: Detected ripple clock \"div_cnt\[24\]\" as buffer" {  } { { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 18 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "div_cnt\[24\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "third_over " "Info: Detected ripple clock \"third_over\" as buffer" {  } { { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 28 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "third_over" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_over " "Info: Detected ripple clock \"second_over\" as buffer" {  } { { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 27 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "second_over" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register last_over register cntfirst\[1\] 67.88 MHz 14.732 ns Internal " "Info: Clock \"clk\" has Internal fmax of 67.88 MHz between source register \"last_over\" and destination register \"cntfirst\[1\]\" (period= 14.732 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.458 ns + Longest register register " "Info: + Longest register to register delay is 2.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns last_over 1 REG LC_X12_Y7_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y7_N1; Fanout = 3; REG Node = 'last_over'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "" { last_over } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.200 ns) 1.116 ns process1~0 2 COMB LC_X12_Y7_N3 3 " "Info: 2: + IC(0.916 ns) + CELL(0.200 ns) = 1.116 ns; Loc. = LC_X12_Y7_N3; Fanout = 3; COMB Node = 'process1~0'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "1.116 ns" { last_over process1~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.591 ns) 2.458 ns cntfirst\[1\] 3 REG LC_X12_Y7_N9 5 " "Info: 3: + IC(0.751 ns) + CELL(0.591 ns) = 2.458 ns; Loc. = LC_X12_Y7_N9; Fanout = 5; REG Node = 'cntfirst\[1\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "1.342 ns" { process1~0 cntfirst[1] } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.791 ns 32.18 % " "Info: Total cell delay = 0.791 ns ( 32.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.667 ns 67.82 % " "Info: Total interconnect delay = 1.667 ns ( 67.82 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "2.458 ns" { last_over process1~0 cntfirst[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.458 ns" { last_over process1~0 cntfirst[1] } { 0.000ns 0.916ns 0.751ns } { 0.000ns 0.200ns 0.591ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-11.565 ns - Smallest " "Info: - Smallest clock skew is -11.565 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.217 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 11.217 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 29 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 29; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "" { clk } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(1.294 ns) 7.096 ns div_cnt\[24\] 2 REG LC_X11_Y4_N7 6 " "Info: 2: + IC(4.670 ns) + CELL(1.294 ns) = 7.096 ns; Loc. = LC_X11_Y4_N7; Fanout = 6; REG Node = 'div_cnt\[24\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "5.964 ns" { clk div_cnt[24] } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.203 ns) + CELL(0.918 ns) 11.217 ns cntfirst\[1\] 3 REG LC_X12_Y7_N9 5 " "Info: 3: + IC(3.203 ns) + CELL(0.918 ns) = 11.217 ns; Loc. = LC_X12_Y7_N9; Fanout = 5; REG Node = 'cntfirst\[1\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "4.121 ns" { div_cnt[24] cntfirst[1] } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns 29.81 % " "Info: Total cell delay = 3.344 ns ( 29.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.873 ns 70.19 % " "Info: Total interconnect delay = 7.873 ns ( 70.19 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "11.217 ns" { clk div_cnt[24] cntfirst[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.217 ns" { clk clk~combout div_cnt[24] cntfirst[1] } { 0.000ns 0.000ns 4.670ns 3.203ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 22.782 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 22.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 29 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 29; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "" { clk } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(1.294 ns) 7.096 ns div_cnt\[24\] 2 REG LC_X11_Y4_N7 6 " "Info: 2: + IC(4.670 ns) + CELL(1.294 ns) = 7.096 ns; Loc. = LC_X11_Y4_N7; Fanout = 6; REG Node = 'div_cnt\[24\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "5.964 ns" { clk div_cnt[24] } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.203 ns) + CELL(1.294 ns) 11.593 ns first_over 3 REG LC_X12_Y7_N3 5 " "Info: 3: + IC(3.203 ns) + CELL(1.294 ns) = 11.593 ns; Loc. = LC_X12_Y7_N3; Fanout = 5; REG Node = 'first_over'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "4.497 ns" { div_cnt[24] first_over } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.291 ns) + CELL(1.294 ns) 16.178 ns second_over 4 REG LC_X12_Y3_N2 5 " "Info: 4: + IC(3.291 ns) + CELL(1.294 ns) = 16.178 ns; Loc. = LC_X12_Y3_N2; Fanout = 5; REG Node = 'second_over'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "4.585 ns" { first_over second_over } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.427 ns) + CELL(1.294 ns) 19.899 ns third_over 5 REG LC_X13_Y10_N9 5 " "Info: 5: + IC(2.427 ns) + CELL(1.294 ns) = 19.899 ns; Loc. = LC_X13_Y10_N9; Fanout = 5; REG Node = 'third_over'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "3.721 ns" { second_over third_over } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.965 ns) + CELL(0.918 ns) 22.782 ns last_over 6 REG LC_X12_Y7_N1 3 " "Info: 6: + IC(1.965 ns) + CELL(0.918 ns) = 22.782 ns; Loc. = LC_X12_Y7_N1; Fanout = 3; REG Node = 'last_over'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "2.883 ns" { third_over last_over } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.226 ns 31.72 % " "Info: Total cell delay = 7.226 ns ( 31.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.556 ns 68.28 % " "Info: Total interconnect delay = 15.556 ns ( 68.28 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "22.782 ns" { clk div_cnt[24] first_over second_over third_over last_over } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "22.782 ns" { clk clk~combout div_cnt[24] first_over second_over third_over last_over } { 0.000ns 0.000ns 4.670ns 3.203ns 3.291ns 2.427ns 1.965ns } { 0.000ns 1.132ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "11.217 ns" { clk div_cnt[24] cntfirst[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.217 ns" { clk clk~combout div_cnt[24] cntfirst[1] } { 0.000ns 0.000ns 4.670ns 3.203ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "22.782 ns" { clk div_cnt[24] first_over second_over third_over last_over } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "22.782 ns" { clk clk~combout div_cnt[24] first_over second_over third_over last_over } { 0.000ns 0.000ns 4.670ns 3.203ns 3.291ns 2.427ns 1.965ns } { 0.000ns 1.132ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 22 -1 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "2.458 ns" { last_over process1~0 cntfirst[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.458 ns" { last_over process1~0 cntfirst[1] } { 0.000ns 0.916ns 0.751ns } { 0.000ns 0.200ns 0.591ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "11.217 ns" { clk div_cnt[24] cntfirst[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.217 ns" { clk clk~combout div_cnt[24] cntfirst[1] } { 0.000ns 0.000ns 4.670ns 3.203ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73_cmp.qrpt" Compiler "seg73" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "22.782 ns" { clk div_cnt[24] first_over second_over third_over last_over } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "22.782 ns" { clk clk~combout div_cnt[24] first_over second_over third_over last_over } { 0.000ns 0.000ns 4.670ns 3.203ns 3.291ns 2.427ns 1.965ns } { 0.000ns 1.132ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0}