buzzer.tan.qmsg

蜂鸣器实验 向蜂鸣器发送一定频率的方波可以使蜂鸣器发出相应的音调

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 12 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register clk_div2\[1\] register clk_div2\[11\] 82.86 MHz 12.069 ns Internal " "Info: Clock \"clk\" has Internal fmax of 82.86 MHz between source register \"clk_div2\[1\]\" and destination register \"clk_div2\[11\]\" (period= 12.069 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.360 ns + Longest register register " "Info: + Longest register to register delay is 11.360 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_div2\[1\] 1 REG LC_X8_Y7_N5 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y7_N5; Fanout = 10; REG Node = 'clk_div2\[1\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "" { clk_div2[1] } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.108 ns) + CELL(0.740 ns) 2.848 ns reduce_or~289 2 COMB LC_X9_Y6_N7 2 " "Info: 2: + IC(2.108 ns) + CELL(0.740 ns) = 2.848 ns; Loc. = LC_X9_Y6_N7; Fanout = 2; COMB Node = 'reduce_or~289'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "2.848 ns" { clk_div2[1] reduce_or~289 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.938 ns) + CELL(0.200 ns) 4.986 ns reduce_or~8 3 COMB LC_X10_Y7_N9 1 " "Info: 3: + IC(1.938 ns) + CELL(0.200 ns) = 4.986 ns; Loc. = LC_X10_Y7_N9; Fanout = 1; COMB Node = 'reduce_or~8'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "2.138 ns" { reduce_or~289 reduce_or~8 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.931 ns) + CELL(0.200 ns) 7.117 ns clk_div2\[0\]~1754 4 COMB LC_X8_Y7_N2 1 " "Info: 4: + IC(1.931 ns) + CELL(0.200 ns) = 7.117 ns; Loc. = LC_X8_Y7_N2; Fanout = 1; COMB Node = 'clk_div2\[0\]~1754'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "2.131 ns" { reduce_or~8 clk_div2[0]~1754 } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 7.622 ns clk_div2\[0\]~1758 5 COMB LC_X8_Y7_N3 1 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 7.622 ns; Loc. = LC_X8_Y7_N3; Fanout = 1; COMB Node = 'clk_div2\[0\]~1758'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "0.505 ns" { clk_div2[0]~1754 clk_div2[0]~1758 } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.710 ns) + CELL(0.200 ns) 8.532 ns clk_div2\[0\]~1759 6 COMB LC_X8_Y7_N0 13 " "Info: 6: + IC(0.710 ns) + CELL(0.200 ns) = 8.532 ns; Loc. = LC_X8_Y7_N0; Fanout = 13; COMB Node = 'clk_div2\[0\]~1759'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "0.910 ns" { clk_div2[0]~1758 clk_div2[0]~1759 } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.068 ns) + CELL(1.760 ns) 11.360 ns clk_div2\[11\] 7 REG LC_X9_Y7_N5 9 " "Info: 7: + IC(1.068 ns) + CELL(1.760 ns) = 11.360 ns; Loc. = LC_X9_Y7_N5; Fanout = 9; REG Node = 'clk_div2\[11\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "2.828 ns" { clk_div2[0]~1759 clk_div2[11] } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.300 ns 29.05 % " "Info: Total cell delay = 3.300 ns ( 29.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.060 ns 70.95 % " "Info: Total interconnect delay = 8.060 ns ( 70.95 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "11.360 ns" { clk_div2[1] reduce_or~289 reduce_or~8 clk_div2[0]~1754 clk_div2[0]~1758 clk_div2[0]~1759 clk_div2[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.360 ns" { clk_div2[1] reduce_or~289 reduce_or~8 clk_div2[0]~1754 clk_div2[0]~1758 clk_div2[0]~1759 clk_div2[11] } { 0.000ns 2.108ns 1.938ns 1.931ns 0.305ns 0.710ns 1.068ns } { 0.000ns 0.740ns 0.200ns 0.200ns 0.200ns 0.200ns 1.760ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.732 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 43 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 43; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "" { clk } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.682 ns) + CELL(0.918 ns) 6.732 ns clk_div2\[11\] 2 REG LC_X9_Y7_N5 9 " "Info: 2: + IC(4.682 ns) + CELL(0.918 ns) = 6.732 ns; Loc. = LC_X9_Y7_N5; Fanout = 9; REG Node = 'clk_div2\[11\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "5.600 ns" { clk clk_div2[11] } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.45 % " "Info: Total cell delay = 2.050 ns ( 30.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.682 ns 69.55 % " "Info: Total interconnect delay = 4.682 ns ( 69.55 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "6.732 ns" { clk clk_div2[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.732 ns" { clk clk~combout clk_div2[11] } { 0.000ns 0.000ns 4.682ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.732 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 43 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 43; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "" { clk } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.682 ns) + CELL(0.918 ns) 6.732 ns clk_div2\[1\] 2 REG LC_X8_Y7_N5 10 " "Info: 2: + IC(4.682 ns) + CELL(0.918 ns) = 6.732 ns; Loc. = LC_X8_Y7_N5; Fanout = 10; REG Node = 'clk_div2\[1\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "5.600 ns" { clk clk_div2[1] } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.45 % " "Info: Total cell delay = 2.050 ns ( 30.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.682 ns 69.55 % " "Info: Total interconnect delay = 4.682 ns ( 69.55 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "6.732 ns" { clk clk_div2[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.732 ns" { clk clk~combout clk_div2[1] } { 0.000ns 0.000ns 4.682ns } { 0.000ns 1.132ns 0.918ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "6.732 ns" { clk clk_div2[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.732 ns" { clk clk~combout clk_div2[11] } { 0.000ns 0.000ns 4.682ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "6.732 ns" { clk clk_div2[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.732 ns" { clk clk~combout clk_div2[1] } { 0.000ns 0.000ns 4.682ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 21 -1 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "11.360 ns" { clk_div2[1] reduce_or~289 reduce_or~8 clk_div2[0]~1754 clk_div2[0]~1758 clk_div2[0]~1759 clk_div2[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.360 ns" { clk_div2[1] reduce_or~289 reduce_or~8 clk_div2[0]~1754 clk_div2[0]~1758 clk_div2[0]~1759 clk_div2[11] } { 0.000ns 2.108ns 1.938ns 1.931ns 0.305ns 0.710ns 1.068ns } { 0.000ns 0.740ns 0.200ns 0.200ns 0.200ns 0.200ns 1.760ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "6.732 ns" { clk clk_div2[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.732 ns" { clk clk~combout clk_div2[11] } { 0.000ns 0.000ns 4.682ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "6.732 ns" { clk clk_div2[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.732 ns" { clk clk~combout clk_div2[1] } { 0.000ns 0.000ns 4.682ns } { 0.000ns 1.132ns 0.918ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk out_bit out_bit_tmp 13.260 ns register " "Info: tco from clock \"clk\" to destination pin \"out_bit\" through register \"out_bit_tmp\" is 13.260 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.732 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 43 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 43; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "" { clk } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.682 ns) + CELL(0.918 ns) 6.732 ns out_bit_tmp 2 REG LC_X10_Y7_N6 4 " "Info: 2: + IC(4.682 ns) + CELL(0.918 ns) = 6.732 ns; Loc. = LC_X10_Y7_N6; Fanout = 4; REG Node = 'out_bit_tmp'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "5.600 ns" { clk out_bit_tmp } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.45 % " "Info: Total cell delay = 2.050 ns ( 30.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.682 ns 69.55 % " "Info: Total interconnect delay = 4.682 ns ( 69.55 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "6.732 ns" { clk out_bit_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.732 ns" { clk clk~combout out_bit_tmp } { 0.000ns 0.000ns 4.682ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.152 ns + Longest register pin " "Info: + Longest register to pin delay is 6.152 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns out_bit_tmp 1 REG LC_X10_Y7_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y7_N6; Fanout = 4; REG Node = 'out_bit_tmp'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "" { out_bit_tmp } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.830 ns) + CELL(2.322 ns) 6.152 ns out_bit 2 PIN PIN_75 0 " "Info: 2: + IC(3.830 ns) + CELL(2.322 ns) = 6.152 ns; Loc. = PIN_75; Fanout = 0; PIN Node = 'out_bit'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "6.152 ns" { out_bit_tmp out_bit } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns 37.74 % " "Info: Total cell delay = 2.322 ns ( 37.74 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.830 ns 62.26 % " "Info: Total interconnect delay = 3.830 ns ( 62.26 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "6.152 ns" { out_bit_tmp out_bit } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.152 ns" { out_bit_tmp out_bit } { 0.000ns 3.830ns } { 0.000ns 2.322ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "6.732 ns" { clk out_bit_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.732 ns" { clk clk~combout out_bit_tmp } { 0.000ns 0.000ns 4.682ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/" "" "6.152 ns" { out_bit_tmp out_bit } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.152 ns" { out_bit_tmp out_bit } { 0.000ns 3.830ns } { 0.000ns 2.322ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 16 17:57:59 2006 " "Info: Processing ended: Thu Feb 16 17:57:59 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}